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ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1
authorLiu Ying <Ying.Liu@freescale.com>
Fri, 13 Apr 2012 10:10:14 +0000 (18:10 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:34:26 +0000 (08:34 +0200)
commita0fe4d3496a7e7c158e72b32518a03e05a8b1405
tree057af23690d75f1e1ad6a04519f7ff70fad8fa6ftree | snapshot
parent5cc13152479b663197de91e749fc566f4d1d6d91commit | diff
ENGR00179647 MX6 clock:Correct LDB DI pclk for MX6Q TO1.1

This patch corrects LDB DI clock's parent clock to
be pll2_pfd_352M for both MX6Q TO1.1 and MX6Q TO1.0
according to ticket TKT071080(0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1).

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
arch/arm/mach-mx6/clock.c diff | blob | history
Linux kernel for KaRo TX COM modules