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ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.
authorRanjani Vaidyanathan <ra5478@freescale.com>
Tue, 27 Aug 2013 22:57:55 +0000 (17:57 -0500)
committerLothar Waßmann <LW@KARO-electronics.de>
Mon, 16 Jun 2014 15:47:49 +0000 (17:47 +0200)
commita1b966335e029134362cb65c77d835ce77506462
tree39d2a0cbfad524c4418843c4765a12238c204dcetree | snapshot
parent9fb4be82d885b62acf9198e2097492880c14402fcommit | diff
ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.

Need to ensure that PLL1 and PLL2 have the enabled bit set even when
the PLL is powered down and disabled.

1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled.
2. PLL2 will be set to bypass and enabled state (can be powered down) in low
power IDLE mode.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
arch/arm/mach-imx/clk-imx6q.c diff | blob | history
arch/arm/mach-imx/clk-imx6sl.c diff | blob | history
arch/arm/mach-imx/clk-pllv3.c diff | blob | history
arch/arm/mach-imx/clk.h diff | blob | history
Linux kernel for KaRo TX COM modules