ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.

ENGR00222257 MX6x-Prime TLB entries before DDR enters self-refresh.

Need to ensure that no page table walk occurs in DDR when it is in
self refresh and its IO pads are floated during suspend.
Hence we need to make sure that the translation of all the
addresses that the suspend code will access is in the TLB before
DDR cannot be accessed anymore.
So do a dummy read of IOMUX, MMDC, SRC and ANATOP regsiters.
Also need to add a dsb to drain all the write buffers before
DDR enters self-refresh.

Also ensure that the LDO bypass enable is reset if an interrupt
is pending before the system enters suspend.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>