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(parent: afff455) | patch
clk: tegra: Fix WARN_ON in PLL_RE registration
authorBill Huang <bilhuang@nvidia.com>
Thu, 18 Jun 2015 21:28:38 +0000 (17:28 -0400)
committerThierry Reding <treding@nvidia.com>
Thu, 17 Dec 2015 12:37:57 +0000 (13:37 +0100)
commita4ca2b2fe7252032022d14b4efd462161c91165b
treeb7752b39cefa957f4e0cbc6821df27c5916d6f5atree | snapshot
parentafff455cf4f2501d30446eefbfd0aecb14b8a0b8commit | diff
clk: tegra: Fix WARN_ON in PLL_RE registration

This fixes two things.

- Read the correct IDDQ register
- Check the correct IDDQ bit position

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
Beck SC1x5 Kernel