]> git.karo-electronics.de Git - karo-tx-linux.git/commit
clk: tegra: allow PLL m,n,p init from SoC files
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Wed, 5 Jun 2013 13:51:25 +0000 (16:51 +0300)
committerMike Turquette <mturquette@linaro.org>
Wed, 12 Jun 2013 00:38:39 +0000 (17:38 -0700)
commitaa6fefde62401a84154161a8026872874a70e4c1
treeb1787ce0bfe3258b9584f04a9ed49f30bfa6e66b
parentc388eee21ad20929f440d6fae94c995791c5818b
clk: tegra: allow PLL m,n,p init from SoC files

The m,n,p fields don't have the same bit offset and width across all PLLs.
This patch allows SoC specific files to indicate the offset and width.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/tegra/clk-pll.c
drivers/clk/tegra/clk.h