ENGR00179685 MX6 clock:Cleanup LDB DI parent clock

ENGR00179685 MX6 clock:Cleanup LDB DI parent clock

According to ticket TKT071080, 0b011 for ldb_dix_clk_sel
field in CCM_CS2CDR is changed from pll3_pfd_540M to
mmdc_ch1 when we change from MX6Q TO1.0 to MX6Q TO1.1.
However, MX6DL uses mmdc_ch1 as LDB DI parent clock.
This patch corrects the LDB DI parent clock setting.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>