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(parent: 17ac8ce) | patch
amd64_edac: Add a fix for Erratum 505
authorBorislav Petkov <borislav.petkov@amd.com>
Mon, 19 Sep 2011 15:34:45 +0000 (17:34 +0200)
committerBorislav Petkov <borislav.petkov@amd.com>
Thu, 22 Sep 2011 11:05:24 +0000 (13:05 +0200)
commitace9290e81aefff6779f7cc4cd9d729760eebea0
treeee533dd16b60e7942b53514ba73e06e1b65786c8tree | snapshot
parent17ac8ce1c3b8cf9c3207d9c510bc833e6dc1f494commit | diff
amd64_edac: Add a fix for Erratum 505

When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
drivers/edac/amd64_edac.c diff | blob | history
Linux kernel for KaRo TX COM modules