ASoC: Coalesce register writes for DAPM sequences

ASoC: Coalesce register writes for DAPM sequences

Reduce the number of register writes we need to set the power state for
a CODEC by coalescing updates to widgets with the same sequence order and
same register into a single write.

This can be a noticable performance improvement with slow or heavily
contended control buses, such as I2C controllers with a low clock
frequency, and is particularly noticable when resuming. It can also
reduce the noticability of and pops and clicks by ensuring that left
and right channels are powered simultaneously if they are in the same
register.

Currently widgets that have events are not coalesced, including PGAs
which may use the volume ramping control.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>