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MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
authorYonghong Song <ysong@broadcom.com>
Sat, 21 Dec 2013 11:22:16 +0000 (16:52 +0530)
committerJohn Crispin <blogic@openwrt.org>
Tue, 14 Jan 2014 20:39:41 +0000 (21:39 +0100)
commitb94d61cd0ba97ee40f06ccf72d0b0f6add265930
tree18ca50aa3cdf5cf860105e2bb6bdce7271cba5d7tree | snapshot
parentf82ad8dc6ed226d27e6f6faec71b1762b3d8e218commit | diff
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII

On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Acked-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
arch/mips/netlogic/common/reset.S diff | blob | history
Linux kernel for KaRo TX COM modules