]> git.karo-electronics.de Git - karo-tx-linux.git/commit
perf, x86: Add cache events for the Pentium-4 PMU
authorLin Ming <ming.m.lin@intel.com>
Thu, 18 Mar 2010 10:33:12 +0000 (18:33 +0800)
committerIngo Molnar <mingo@elte.hu>
Thu, 18 Mar 2010 16:04:02 +0000 (17:04 +0100)
commitcb7d6b5053e86598735d9af19930f5929f007b7f
treeb707d913470443c05bd637d4b7fbab3926e0ba1c
parentf34edbc1cdb0f8f83d94e1d668dd6e41abf0defb
perf, x86: Add cache events for the Pentium-4 PMU

Move the HT bit setting code from p4_pmu_event_map to
p4_hw_config. So the cache events can get HT bit set correctly.

Tested on my P4 desktop, below 6 cache events work:

 L1-dcache-load-misses
 LLC-load-misses
 dTLB-load-misses
 dTLB-store-misses
 iTLB-loads
 iTLB-load-misses

Signed-off-by: Lin Ming <ming.m.lin@intel.com>
Reviewed-by: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1268908392.13901.128.camel@minggr.sh.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/include/asm/msr-index.h
arch/x86/include/asm/perf_event_p4.h
arch/x86/kernel/cpu/perf_event_p4.c