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(parent: c0f3b86) | patch
mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly
authorEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Mon, 12 Aug 2013 17:14:48 +0000 (14:14 -0300)
committerDavid Woodhouse <David.Woodhouse@intel.com>
Fri, 30 Aug 2013 20:34:51 +0000 (21:34 +0100)
commitcd9d11820f4232856d6254a29fbb9c4f51a981c2
tree905bc413c07bc79bf0b6d72b974ee81c03e5d34atree | snapshot
parentc0f3b8643a6fa2461d70760ec49d21d2b031d611commit | diff
mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly

When ECC is not selected, the ECC enable bit must be cleared
in the NAND control register. Same applies to DMA.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
drivers/mtd/nand/pxa3xx_nand.c diff | blob | history
Beck SC1x5 Kernel