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ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.
authorFugang Duan <B38611@freescale.com>
Wed, 8 Feb 2012 03:39:25 +0000 (11:39 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:33:56 +0000 (08:33 +0200)
commitce9215ecddbb523af30ad3d982dda33a605b6b08
treed7cad49bd1d7728514bd9ca5c2ec0309dce3aa16tree | snapshot
parent3d2b0861572070160c19a641728b9313664e4ae6commit | diff
ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.

Default use RMII 50MHz clock for ts_clk.
Test result:
Enet work fine at 100/1000Mbps in TO1.1 and Rigel.
IEEE 1588 timestamp is convergent for 25M & 50M & 100MHz
timestamp clock.

Signed-off-by: Fugang Duan <B38611@freescale.com>
drivers/net/fec.c diff | blob | history
drivers/net/fec_1588.c diff | blob | history
drivers/net/fec_1588.h diff | blob | history
Linux kernel for KaRo TX COM modules