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(parent: 27efeb6) | patch
x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs
authorAndi Kleen <ak@suse.de>
Wed, 30 Jan 2008 12:32:37 +0000 (13:32 +0100)
committerIngo Molnar <mingo@elte.hu>
Wed, 30 Jan 2008 12:32:37 +0000 (13:32 +0100)
commitde4218634e3df6d73a3e6cdfdf3a17fa3bc7e013
treedf7438f5ee81fc7c93f5e9ab3f4249a5afc3d31ctree | snapshot
parent27efeb67714608b28c0b213cceb6080749435c6bcommit | diff
x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs

According to AMD RDTSC can be synchronized through MFENCE.
Implement the necessary CPUID bit for that.

Cc: andreas.herrmann3@amd.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/kernel/cpu/amd.c diff | blob | history
arch/x86/kernel/setup_64.c diff | blob | history
include/asm-x86/cpufeature.h diff | blob | history
Beck SC1x5 Kernel