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MIPS: Netlogic: Avoid unnecessary cache flushes
authorJayachandran C <jayachandranc@netlogicmicro.com>
Tue, 23 Aug 2011 08:05:51 +0000 (13:35 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 15 Nov 2011 23:59:53 +0000 (23:59 +0000)
commitdf95f40d6df68340e18e42180c83d69df0e944a9
tree91d7c4cc53ca457a92500883e7997281d4bea242tree | snapshot
parent3c03574c13c96342219915488b42df7933a078a7commit | diff
MIPS: Netlogic: Avoid unnecessary cache flushes

XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h diff | blob | history
Linux kernel for KaRo TX COM modules