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ARM: dt: tegra seaboard: fix I2C2 SCL rate
authorStephen Warren <swarren@nvidia.com>
Thu, 26 Apr 2012 17:19:03 +0000 (11:19 -0600)
committerStephen Warren <swarren@nvidia.com>
Thu, 26 Apr 2012 18:24:36 +0000 (12:24 -0600)
commite0b50a5833e31d3b402e999a0c9fc5fa274445d8
tree36721d94a59a101a2e91f01427a606913e340f34tree | snapshot
parentd8fad4ab6f060bb6216cacfbe5af2d1d9ec0a015commit | diff
ARM: dt: tegra seaboard: fix I2C2 SCL rate

This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/boot/dts/tegra-seaboard.dts diff | blob | history
Linux kernel for KaRo TX COM modules