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(parent: 9a7a076) | patch
x86/tsc: Add missing Cherrytrail frequency to the table
authorJeremy Compostella <jeremy.compostella@intel.com>
Wed, 11 May 2016 15:23:34 +0000 (17:23 +0200)
committerThomas Gleixner <tglx@linutronix.de>
Thu, 12 May 2016 12:27:14 +0000 (14:27 +0200)
commite2724e9d969294879936daf7833d4adda26c8efc
tree8fe694e2996430f124a4ffe25c206a4136e9e733tree | snapshot
parent9a7a076e8e4ffcfec05e3cafe4c4e31d41ddbaa0commit | diff
x86/tsc: Add missing Cherrytrail frequency to the table

Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4
means that the CPU reference clock runs at 80MHz.  Add this missing
frequency to the table.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Link: http://lkml.kernel.org/r/87y47gty89.fsf@intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
arch/x86/kernel/tsc_msr.c diff | blob | history
Beck SC1x5 Kernel