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ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.
authorFugang Duan <B38611@freescale.com>
Wed, 8 Feb 2012 03:39:25 +0000 (11:39 +0800)
committerOliver Wendt <ow@karo-electronics.de>
Mon, 30 Sep 2013 12:10:49 +0000 (14:10 +0200)
commite4523ca9d6858ce33deba4cfb62991665ec96177
treed7cad49bd1d7728514bd9ca5c2ec0309dce3aa16tree | snapshot
parent6ff2140fd701de676c1fee1449589b8e3cfc216acommit | diff
ENGR00172274-02 - IEEE-1588: rework ts_clk in MX6 ARIK CPU board.

Default use RMII 50MHz clock for ts_clk.
Test result:
Enet work fine at 100/1000Mbps in TO1.1 and Rigel.
IEEE 1588 timestamp is convergent for 25M & 50M & 100MHz
timestamp clock.

Signed-off-by: Fugang Duan <B38611@freescale.com>
drivers/net/fec.c diff | blob | history
drivers/net/fec_1588.c diff | blob | history
drivers/net/fec_1588.h diff | blob | history
Linux kernel for KaRo TX COM modules