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(parent: d84bc15) | patch
ENGR00220496 MX6SL:Add low power IDLE mode optimizations.
authorRanjani Vaidyanathan <ra5478@freescale.com>
Thu, 26 Jul 2012 18:53:28 +0000 (13:53 -0500)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:35:15 +0000 (08:35 +0200)
commite52518152bb780c1e028deadab56904e09f6173b
treef33bb22563977938d689e7dd3abfefc932bf63e1tree | snapshot
parentd84bc157cca00f62fd7d4958e64d5bab56392c74commit | diff
ENGR00220496 MX6SL:Add low power IDLE mode optimizations.

Add support for DDR freq change code in IRAM.
Change PLL2 to bypass mode so that DDR is running off 24MHz OSC
directly.
ARM is now sourced from PLL1 (running at 800MHz) in this mode.
This is required for the next step in IDLE mode optmization
where all PLLs will be disabled when ARM enters WFI.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
arch/arm/mach-mx6/Makefile diff | blob | history
arch/arm/mach-mx6/bus_freq.c diff | blob | history
arch/arm/mach-mx6/clock_mx6sl.c diff | blob | history
arch/arm/mach-mx6/irq.c diff | blob | history
arch/arm/mach-mx6/mx6_anatop_regulator.c diff | blob | history
arch/arm/mach-mx6/mx6sl_ddr.S [new file with mode: 0644] blob
Linux kernel for KaRo TX COM modules