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(parent: 4177120) | patch
ENGR00224476 pgc: fix display power gating causes PxP processing timeout
authorRobby Cai <R63905@freescale.com>
Wed, 12 Sep 2012 06:32:34 +0000 (14:32 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:35:26 +0000 (08:35 +0200)
commite5b6492e56e64f30cb6ff8406c28508c5e2aa541
treec80d1f59c8bfa9c934a8abd67d192d3246a9eb44tree | snapshot
parent4177120a6154058e4b54871116bbea483094f0edcommit | diff
ENGR00224476 pgc: fix display power gating causes PxP processing timeout

The root-cause is PxP need the clock to be on for synchronous reset.
This patch turned on PXP axi clock, and EPDC/LCDIF pix clock, and
EPDC/LCDIF axi clock before power up. The driver codes can guarantee
the clock setting be restored to the one before suspend.

Signed-off-by: Robby Cai <R63905@freescale.com>
arch/arm/mach-mx6/pm.c diff | blob | history
Linux kernel for KaRo TX COM modules