ENGR00173585: MX6: Added WAIT mode workaround for MX6Q TO1.1

ENGR00173585: MX6: Added WAIT mode workaround for MX6Q TO1.1

There is small window where an interrupt can occur when the SOC is
in the process of entering WAIT mode. The ARM core responds to this
interrupt and can access the internal memories when their clocks are
disabled.
To avoid crashes generated due to this, WFI code should be executed
from non-cacheable IRAM and enough delay should added after the
WFI so that accesses to memories are prevented.

This workaround assumes that all interrupts are routed to CPU0 only.
This workaround is applicable to iMX6DL/Solo also.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>