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ENGR00172360-2 - MXC HDMI: New TO1.1 PLL5/PLL4 dividers not set up in clock code
authorDanny Nold <dannynold@freescale.com>
Thu, 19 Jan 2012 20:56:33 +0000 (14:56 -0600)
committerOliver Wendt <ow@karo-electronics.de>
Mon, 30 Sep 2013 12:10:39 +0000 (14:10 +0200)
commitef1c3a55aec7d2be39ea8772c3f77ae5388c9514
tree0fce8c1d3efdc845c1e6e4c23fe63ecfd36f69b6tree | snapshot
parent7f43b97310e097c01beb592710ef7ea643205df8commit | diff
ENGR00172360-2 - MXC HDMI: New TO1.1 PLL5/PLL4 dividers not set up in clock code

Due to the use of some higher frequencies for HDMI video modes, the
IPU clock set/get/round functions need to use 64-bit variables
for clock calculations instead of 32-bit variables.

Signed-off-by: Danny Nold <dannynold@freescale.com>
drivers/mxc/ipu3/ipu_disp.c diff | blob | history
Linux kernel for KaRo TX COM modules