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(parent: 841c61c) | patch
cciss: add half second delay to PCI PM reset code
authorMike Miller <mike.miller@hp.com>
Wed, 5 Oct 2011 00:42:41 +0000 (11:42 +1100)
committerStephen Rothwell <sfr@canb.auug.org.au>
Thu, 6 Oct 2011 05:48:57 +0000 (16:48 +1100)
commitf01fa0c931c59416f33488c51901d75a182c5b6c
treeb69e8a4a5d4b3fa9f314259da5b35723d484448dtree | snapshot
parent841c61ce7b5f2c89387f48dd2f8ee2f66801f2cacommit | diff
cciss: add half second delay to PCI PM reset code

After using PCI Power Management to reset the Smart Array in kdump kernels
we need some delay.  Otherwise we may think the board failed to reset and
bail out.  This affects all users with a Smart Array P600.

Signed-off-by: Mike Miller <mike.miller@hp.com>
Cc: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Andrew Morton <akpm@google.com>
drivers/block/cciss.c diff | blob | history
Linux kernel for KaRo TX COM modules