ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M

ENGR00174152 i.mx6/clock: set ddr clock parent to pll2_mfd_400M

on i.mx6dl, DDR clock is sourcing from pll2_mfd_400M, so, we need
set DDR/periph_clk parent to pll2_mfd_400M during clock init, which
will setup the clock usecount of pll2_mfd_400M correctly, otherwise,
when all the child device with clock source from pll2_mfd_400M turn
off, the pll2_mfd_400M will turns off automaticly, which will cause
system hang due to DDR clock is off when code is runing on it.

Signed-off-by: Jason Liu <r64343@freescale.com>