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(parent: 7f2ea38) | patch
clk: sunxi: Add PLL3 clock
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Wed, 23 Mar 2016 16:38:26 +0000 (17:38 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 21 Apr 2016 22:29:23 +0000 (00:29 +0200)
commitfa4d0ca104bfdcda7b7e2bac855b358f302fd310
tree14c68c6b45413a4281a7d53af3b84564400a4bf1tree | snapshot
parent7f2ea3847d47d49929d41573a3b26c80ddebbef5commit | diff
clk: sunxi: Add PLL3 clock

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
PLL7, clocked from a 3MHz oscillator, that drives the display related
clocks (GPU, display engine, TCON, etc.)

Add a driver for it.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/Makefile diff | blob | history
drivers/clk/sunxi/clk-sun4i-pll3.c [new file with mode: 0644] blob
Beck SC1x5 Kernel