ENGR00288407 pcie: add pcie ep rc validation system

ENGR00288407 pcie: add pcie ep rc validation system

HW setup:
* Two i.MX6Q SD boards, one is used as PCIe RC, the other
is used as PCIe EP. Connected by 2*mini_PCIe to standard_PCIe
adaptors, 2*PEX cable adaptors, One PCIe cable.

SW setup:
* When build RC image, make sure that
  CONFIG_IMX_PCIE=y
  # CONFIG_EP_MODE_IN_EP_RC_SYS is not set
  # CONFIG_EP_SELF_IO_TEST is not set
  CONFIG_RC_MODE_IN_EP_RC_SYS=y
* When build EP image,(enable if you want ep do self IO test):
  CONFIG_EP_MODE_IN_EP_RC_SYS=y
  CONFIG_EP_SELF_IO_TEST=y
  # CONFIG_RC_MODE_IN_EP_RC_SYS is not set

Features:
* Set-up link between RC and EP by their stand-alone
125MHz running internally.
* In EP's system, EP can access the reserved ddr memory
(default address:0x40000000) of PCIe RC's system, by the
interconnection between PCIe EP and PCIe RC.
* add the configuration methods in the EP side, used to
configure the start address and the size of the reserved
RC's memory window.
- cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info
- echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set
- echo 0x800000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set
* provide one example, howto configure the bar# and so on, when
* pcie ep emaluates one memory ram ep device

Throughput:
* To Be fine-tuned.

NOTE:
* boot up EP platform firstly, then boot up RC platform.

Signed-off-by: Richard Zhu <r65037@freescale.com>