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(parent: 6b7200f) | patch
staging: tidspbridge: MMU2 registers are limited to 32-bit data access
authorVladimir Zapolskiy <vz@mleia.com>
Wed, 19 Oct 2011 19:39:12 +0000 (22:39 +0300)
committerGreg Kroah-Hartman <gregkh@suse.de>
Wed, 19 Oct 2011 20:42:49 +0000 (13:42 -0700)
commitfcde2bf0b9a0581db9fe5382e0c90f526c011114
tree58569442130b97413eb27b98f35e6d374a3c4800tree | snapshot
parent6b7200fe0a59d7bda59e9e028b235b25a137dff9commit | diff
staging: tidspbridge: MMU2 registers are limited to 32-bit data access

According to OMAP3 TRM access to MMU registers shall be strictly 32-bit
aligned.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
drivers/staging/tidspbridge/hw/hw_mmu.c diff | blob | history
Beck SC1x5 Kernel