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drm: rcar-du: Fix H/V sync signal polarity configuration
authorKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Mon, 16 May 2016 02:28:15 +0000 (11:28 +0900)
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Mon, 14 Nov 2016 23:44:50 +0000 (01:44 +0200)
commitfd1adef3bff0663c5ac31b45bc4a05fafd43d19b
tree4e8895caca0db0d50f0551e4c134a6ba1cc99f90tree | snapshot
parent9cdced8a39c04cf798ddb2a27cb5952f7d39f633commit | diff
drm: rcar-du: Fix H/V sync signal polarity configuration

The VSL and HSL bits in the DSMR register set the corresponding
horizontal and vertical sync signal polarity to active high. The code
got it the wrong way around, fix it.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
drivers/gpu/drm/rcar-du/rcar_du_crtc.c diff | blob | history
Beck SC1x5 Kernel