]> git.karo-electronics.de Git - linux-beck.git/commit
MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs
authorAndrew Bresticker <abrestic@chromium.org>
Thu, 18 Sep 2014 21:47:13 +0000 (14:47 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 24 Nov 2014 06:44:53 +0000 (07:44 +0100)
commitff1e29ade4c677c24ee972549d20f07e466d50bf
tree3e22a0a90b8b5163e24a4d21e4cc3eb957e6f772
parenta669efc4a3b49de9226b280bb683f5b1d5a5d143
MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs

Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs.
Since systems using CPS must also have a GIC, which is responsible for
routing all external interrupts and can map them to any hardware interrupt
vector, enable the remaining vectors.  The two software interrupt vectors
are left disabled since they are not used with CPS.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7803/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/smp-cps.c