Rather than rely on explicit initialization order called from SoC setup
code, use a plain initcall and rely on initcall ordering to take care of
dependencies.
This driver exposes some functionality (querying the chip ID) needed at
very early stages of the boot process. An early initcall is good enough
provided that some of the dependencies are deferred to later stages. To
make sure any abuses are easily caught, output a warning message if the
chip ID is queried while it can't be read yet.
Signed-off-by: Thierry Reding <treding@nvidia.com>
static void __init tegra_init_early(void)
{
of_register_trusted_foundations();
static void __init tegra_init_early(void)
{
of_register_trusted_foundations();
tegra_cpu_reset_handler_init();
tegra_powergate_init();
}
tegra_cpu_reset_handler_init();
tegra_powergate_init();
}
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/io.h>
+#include <soc/tegra/common.h>
#include <soc/tegra/fuse.h>
#include "fuse.h"
#include <soc/tegra/fuse.h>
#include "fuse.h"
return device_create_bin_file(dev, &fuse_bin_attr);
}
return device_create_bin_file(dev, &fuse_bin_attr);
}
-void __init tegra_init_fuse(void)
+static int __init tegra_init_fuse(void)
{
struct device_node *np;
void __iomem *car_base;
{
struct device_node *np;
void __iomem *car_base;
+ if (!soc_is_tegra())
+ return 0;
+
tegra_init_apbmisc();
np = of_find_matching_node(NULL, car_match);
tegra_init_apbmisc();
np = of_find_matching_node(NULL, car_match);
iounmap(car_base);
} else {
pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
iounmap(car_base);
} else {
pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
}
if (tegra_get_chip_id() == TEGRA20)
}
if (tegra_get_chip_id() == TEGRA20)
tegra_sku_info.core_process_id);
pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
tegra_sku_info.core_process_id);
pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
+early_initcall(tegra_init_fuse);
u8 tegra_get_chip_id(void)
{
u8 tegra_get_chip_id(void)
{
- u32 id = tegra_read_chipid();
+ if (!apbmisc_base) {
+ WARN(1, "Tegra Chip ID not yet available\n");
+ return 0;
+ }
- return (id >> 8) & 0xff;
+ return (tegra_read_chipid() >> 8) & 0xff;
}
u32 tegra_read_straps(void)
}
u32 tegra_read_straps(void)
u32 tegra_read_straps(void);
u32 tegra_read_chipid(void);
u32 tegra_read_straps(void);
u32 tegra_read_chipid(void);
-void tegra_init_fuse(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);
extern struct tegra_sku_info tegra_sku_info;
int tegra_fuse_readl(unsigned long offset, u32 *value);
extern struct tegra_sku_info tegra_sku_info;