+/*
+ * write_sdrc_timings -
+ * - Takes CS and associated timings and initalize SDRAM
+ * - Test CS to make sure it's OK for use
+ */
+static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
+ u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+{
+ /* Setup timings we got from the board. */
+ writel(mcfg, &sdrc_base->cs[cs].mcfg);
+ writel(ctrla, &sdrc_actim_base->ctrla);
+ writel(ctrlb, &sdrc_actim_base->ctrlb);
+ writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(mr, &sdrc_base->cs[cs].mr);
+
+ /*
+ * Test ram in this bank
+ * Disable if bad or not present
+ */
+ if (!mem_ok(cs))
+ writel(0, &sdrc_base->cs[cs].mcfg);
+}
+