Code cleanup. A read-after-write construct is present in the code to ensure
write order for certain Broadcom chips. Those chips are: bcm4706, bcm4716,
bcm4717, bcm4718. All these chips contain a MIPS processor. This patch gets
rid of several #ifdef __mips__ sections by defining a new macro in a header
file. This patch does not introduce behavioral changes and is purely meant
for code cleanup. The __mips__ define will be made more specific in a future
patch.
Signed-off-by: Roland Vossen <rvossen@broadcom.com>
Reviewed-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
if ((D11REV_GE(pi->sh->corerev, 24)) ||
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
if ((D11REV_GE(pi->sh->corerev, 24)) ||
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
- W_REG(&pi->regs->radioregaddr, addr);
-#ifdef __mips__
- (void)R_REG(&pi->regs->radioregaddr);
-#endif
+ W_REG_FLUSH(&pi->regs->radioregaddr, addr);
data = R_REG(&pi->regs->radioregdata);
} else {
data = R_REG(&pi->regs->radioregdata);
} else {
- W_REG(&pi->regs->phy4waddr, addr);
-#ifdef __mips__
- (void)R_REG(&pi->regs->phy4waddr);
-#endif
+ W_REG_FLUSH(&pi->regs->phy4waddr, addr);
#ifdef __ARM_ARCH_4T__
__asm__(" .align 4 ");
#ifdef __ARM_ARCH_4T__
__asm__(" .align 4 ");
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
- W_REG(&pi->regs->radioregaddr, addr);
-#ifdef __mips__
- (void)R_REG(&pi->regs->radioregaddr);
-#endif
+ W_REG_FLUSH(&pi->regs->radioregaddr, addr);
W_REG(&pi->regs->radioregdata, val);
} else {
W_REG(&pi->regs->radioregdata, val);
} else {
- W_REG(&pi->regs->phy4waddr, addr);
-#ifdef __mips__
- (void)R_REG(&pi->regs->phy4waddr);
-#endif
+ W_REG_FLUSH(&pi->regs->phy4waddr, addr);
W_REG(&pi->regs->phy4wdatalo, val);
}
W_REG(&pi->regs->phy4wdatalo, val);
}
if (D11REV_GE(pi->sh->corerev, 24)) {
u32 b0, b1, b2;
if (D11REV_GE(pi->sh->corerev, 24)) {
u32 b0, b1, b2;
- W_REG(&pi->regs->radioregaddr, 0);
-#ifdef __mips__
- (void)R_REG(&pi->regs->radioregaddr);
-#endif
+ W_REG_FLUSH(&pi->regs->radioregaddr, 0);
b0 = (u32) R_REG(&pi->regs->radioregdata);
b0 = (u32) R_REG(&pi->regs->radioregdata);
- W_REG(&pi->regs->radioregaddr, 1);
-#ifdef __mips__
- (void)R_REG(&pi->regs->radioregaddr);
-#endif
+ W_REG_FLUSH(&pi->regs->radioregaddr, 1);
b1 = (u32) R_REG(&pi->regs->radioregdata);
b1 = (u32) R_REG(&pi->regs->radioregdata);
- W_REG(&pi->regs->radioregaddr, 2);
-#ifdef __mips__
- (void)R_REG(&pi->regs->radioregaddr);
-#endif
+ W_REG_FLUSH(&pi->regs->radioregaddr, 2);
b2 = (u32) R_REG(&pi->regs->radioregdata);
id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
& 0xf);
} else {
b2 = (u32) R_REG(&pi->regs->radioregdata);
id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
& 0xf);
} else {
- W_REG(&pi->regs->phy4waddr, RADIO_IDCODE);
-#ifdef __mips__
- (void)R_REG(&pi->regs->phy4waddr);
-#endif
+ W_REG_FLUSH(&pi->regs->phy4waddr, RADIO_IDCODE);
id = (u32) R_REG(&pi->regs->phy4wdatalo);
id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
}
id = (u32) R_REG(&pi->regs->phy4wdatalo);
id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
}
- W_REG(®s->phyregaddr, addr);
-#ifdef __mips__
- (void)R_REG(®s->phyregaddr);
-#endif
+ W_REG_FLUSH(®s->phyregaddr, addr);
pi->phy_wreg = 0;
return R_REG(®s->phyregdata);
pi->phy_wreg = 0;
return R_REG(®s->phyregdata);
regs = pi->regs;
#ifdef __mips__
regs = pi->regs;
#ifdef __mips__
- W_REG(®s->phyregaddr, addr);
- (void)R_REG(®s->phyregaddr);
+ W_REG_FLUSH(®s->phyregaddr, addr);
W_REG(®s->phyregdata, val);
if (addr == 0x72)
(void)R_REG(®s->phyregdata);
W_REG(®s->phyregdata, val);
if (addr == 0x72)
(void)R_REG(®s->phyregdata);
- W_REG(®s->phyregaddr, addr);
-#ifdef __mips__
- (void)R_REG(®s->phyregaddr);
-#endif
+ W_REG_FLUSH(®s->phyregaddr, addr);
W_REG(®s->phyregdata, (R_REG(®s->phyregdata) & val));
pi->phy_wreg = 0;
W_REG(®s->phyregdata, (R_REG(®s->phyregdata) & val));
pi->phy_wreg = 0;
- W_REG(®s->phyregaddr, addr);
-#ifdef __mips__
- (void)R_REG(®s->phyregaddr);
-#endif
+ W_REG_FLUSH(®s->phyregaddr, addr);
W_REG(®s->phyregdata, (R_REG(®s->phyregdata) | val));
pi->phy_wreg = 0;
W_REG(®s->phyregdata, (R_REG(®s->phyregdata) | val));
pi->phy_wreg = 0;
- W_REG(®s->phyregaddr, addr);
-#ifdef __mips__
- (void)R_REG(®s->phyregaddr);
-#endif
+ W_REG_FLUSH(®s->phyregaddr, addr);
W_REG(®s->phyregdata,
((R_REG(®s->phyregdata) & ~mask) | (val & mask)));
W_REG(®s->phyregdata,
((R_REG(®s->phyregdata) & ~mask) | (val & mask)));
} while (0)
#endif /* __BIG_ENDIAN */
} while (0)
#endif /* __BIG_ENDIAN */
+#ifdef __mips__
+/*
+ * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder
+ * transactions. As a fix, a read after write is performed on certain places
+ * in the code. Older chips and the newer 5357 family don't require this fix.
+ */
+#define W_REG_FLUSH(r, v) ({ W_REG((r), (v)); (void)R_REG(r); })
+#else
+#define W_REG_FLUSH(r, v) W_REG((r), (v))
+#endif /* __mips__ */
+
#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))