since we now can include all soc specific headers at once we do not
need the ifdeffery anymore.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
CCR_ACRPT, DMA_CCR(channel));
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
CCR_ACRPT, DMA_CCR(channel));
if ((cpu_is_mx21() || cpu_is_mx27()) &&
imxdma->sg && imx_dma_hw_chain(imxdma)) {
imxdma->sg = sg_next(imxdma->sg);
if ((cpu_is_mx21() || cpu_is_mx27()) &&
imxdma->sg && imx_dma_hw_chain(imxdma)) {
imxdma->sg = sg_next(imxdma->sg);
imxdma->in_use = 1;
local_irq_restore(flags);
imxdma->in_use = 1;
local_irq_restore(flags);
}
EXPORT_SYMBOL(imx_dma_disable);
}
EXPORT_SYMBOL(imx_dma_disable);
static void imx_dma_watchdog(unsigned long chno)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
static void imx_dma_watchdog(unsigned long chno)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
if (imxdma->err_handler)
imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
}
if (imxdma->err_handler)
imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
}
static irqreturn_t dma_err_handler(int irq, void *dev_id)
{
static irqreturn_t dma_err_handler(int irq, void *dev_id)
{
if (cpu_is_mx21() || cpu_is_mx27())
dma_err_handler(irq, dev_id);
if (cpu_is_mx21() || cpu_is_mx27())
dma_err_handler(irq, dev_id);
disr = imx_dmav1_readl(DMA_DISR);
disr = imx_dmav1_readl(DMA_DISR);
imxdma->name = name;
local_irq_restore(flags); /* request_irq() can block */
imxdma->name = name;
local_irq_restore(flags); /* request_irq() can block */
if (cpu_is_mx21() || cpu_is_mx27()) {
ret = request_irq(MX2x_INT_DMACH0 + channel,
dma_irq_handler, 0, "DMA", NULL);
if (cpu_is_mx21() || cpu_is_mx27()) {
ret = request_irq(MX2x_INT_DMACH0 + channel,
dma_irq_handler, 0, "DMA", NULL);
imxdma->watchdog.function = &imx_dma_watchdog;
imxdma->watchdog.data = channel;
}
imxdma->watchdog.function = &imx_dma_watchdog;
imxdma->watchdog.data = channel;
}
imx_dma_disable(channel);
imxdma->name = NULL;
imx_dma_disable(channel);
imxdma->name = NULL;
if (cpu_is_mx21() || cpu_is_mx27())
free_irq(MX2x_INT_DMACH0 + channel, NULL);
if (cpu_is_mx21() || cpu_is_mx27())
free_irq(MX2x_INT_DMACH0 + channel, NULL);
local_irq_restore(flags);
}
local_irq_restore(flags);
}
if (cpu_is_mx1())
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
if (cpu_is_mx1())
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
- else
-#endif
-#ifdef CONFIG_MACH_MX21
- if (cpu_is_mx21())
+ else if (cpu_is_mx21())
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
- else
-#endif
-#ifdef CONFIG_MACH_MX27
- if (cpu_is_mx27())
+ else if (cpu_is_mx27())
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
else
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
else
return 0;
dma_clk = clk_get(NULL, "dma");
return 0;
dma_clk = clk_get(NULL, "dma");
/* reset DMA module */
imx_dmav1_writel(DCR_DRST, DMA_DCR);
/* reset DMA module */
imx_dmav1_writel(DCR_DRST, DMA_DCR);
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
if (ret) {
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
if (ret) {
/* enable DMA module */
imx_dmav1_writel(DCR_DEN, DMA_DCR);
/* enable DMA module */
imx_dmav1_writel(DCR_DEN, DMA_DCR);