Not all hardcoded values have been replaced as this made the code quite
unreadable. IMHO this compromise serves the purpose of readability.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
rtr = frame->can_id & CAN_RTR_FLAG;
rtr = frame->can_id & CAN_RTR_FLAG;
+ /* RTR is always the lowest bit of interest, then IDs follow */
if (frame->can_id & CAN_EFF_FLAG) {
if (frame->can_id & CAN_EFF_FLAG) {
- can_id = (frame->can_id & CAN_EFF_MASK) << 1;
+ can_id = (frame->can_id & CAN_EFF_MASK)
+ << (MSCAN_EFF_RTR_SHIFT + 1);
+ can_id |= 1 << MSCAN_EFF_RTR_SHIFT;
out_be16(®s->tx.idr3_2, can_id);
can_id >>= 16;
out_be16(®s->tx.idr3_2, can_id);
can_id >>= 16;
- can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0) | (3 << 3);
+ /* EFF_FLAGS are inbetween the IDs :( */
+ can_id = (can_id & 0x7) | ((can_id << 2) & 0xffe0)
+ | MSCAN_EFF_FLAGS;
- can_id = (frame->can_id & CAN_SFF_MASK) << 5;
+ can_id = (frame->can_id & CAN_SFF_MASK)
+ << (MSCAN_SFF_RTR_SHIFT + 1);
+ can_id |= 1 << MSCAN_SFF_RTR_SHIFT;
}
out_be16(®s->tx.idr1_0, can_id);
}
out_be16(®s->tx.idr1_0, can_id);
/* MSCAN Miscellaneous Register (CANMISC) bits */
#define MSCAN_BOHOLD 0x01
/* MSCAN Miscellaneous Register (CANMISC) bits */
#define MSCAN_BOHOLD 0x01
+/* MSCAN Identifier Register (IDR) bits */
+#define MSCAN_SFF_RTR_SHIFT 4
+#define MSCAN_EFF_RTR_SHIFT 0
+#define MSCAN_EFF_FLAGS 0x18 /* IDE + SRR */
+
#ifdef MSCAN_FOR_MPC5200
#define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
#define _MSCAN_RESERVED_DSR_SIZE 2
#ifdef MSCAN_FOR_MPC5200
#define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
#define _MSCAN_RESERVED_DSR_SIZE 2