Fix tg3_set_power_state to drive GPIOs properly based on the
TG3_FLAG_EEPROM_WRITE_PROTECT flag. Some delays are also added after D0
and D3 power state changes.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
pci_write_config_word(tp->pdev,
pm + PCI_PM_CTRL,
power_control);
pci_write_config_word(tp->pdev,
pm + PCI_PM_CTRL,
power_control);
- tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
- udelay(100);
+ udelay(100); /* Delay after power state change */
+
+ /* Switch out of Vaux if it is not a LOM */
+ if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
+ tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
+ udelay(100);
+ }
/* Finally, set the new power state. */
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
/* Finally, set the new power state. */
pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
+ udelay(100); /* Delay after power state change */
tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);