IIM:
- Homogenize prg_p naming (the reference manuals are not always self-consistent
for that).
- Add missing SCSx and bank registers.
- Fix the number of banks on i.MX53.
OCOTP:
- Rename iim to ocotp in order to avoid confusion.
- Rename fuse_data to read_fuse_data, and sticky to sw_sticky, according to the
reference manual.
- Merge the existing spinoff gp1 fuse definition on i.MX6.
- Fix the number of banks on i.MX6.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Stefano Babic <sbabic@denx.de>
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- struct fuse_bank *bank = &iim->bank[4];
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[4];
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
struct fuse_bank4_regs *fuse =
(struct fuse_bank4_regs *)bank->fuse_regs;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
- u32 res1[0x1f5];
+ u32 iim_prg_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+ u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
-/* IIM Control Registers */
+/* IIM control registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res1[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
};
/* General Purpose Timer (GPT) registers */
};
/* General Purpose Timer (GPT) registers */
u32 sdat;
u32 prev;
u32 srev;
u32 sdat;
u32 prev;
u32 srev;
u32 scs0;
u32 scs1;
u32 scs2;
u32 scs0;
u32 scs1;
u32 scs2;
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
+#elif defined(CONFIG_MX53)
+ } bank[5];
+#endif
};
struct fuse_bank0_regs {
};
struct fuse_bank0_regs {
#define CHIP_REV_1_0 0x10
#define IRAM_SIZE 0x00040000
#define CHIP_REV_1_0 0x10
#define IRAM_SIZE 0x00040000
-#define IMX_IIM_BASE OCOTP_BASE_ADDR
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#define FEC_QUIRK_ENET_MAC
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-/* OCOTP Registers */
-struct ocotp_regs {
- u32 reserved[0x198];
- u32 gp1; /* 0x660 */
-};
-
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
u32 ctrl;
u32 ctrl_set;
u32 ctrl_clr;
u32 ctrl;
u32 ctrl_set;
u32 ctrl_clr;
u32 rsvd1[3];
u32 read_ctrl;
u32 rsvd2[3];
u32 rsvd1[3];
u32 read_ctrl;
u32 rsvd2[3];
u32 rsvd4[3];
u32 scs;
u32 scs_set;
u32 rsvd4[3];
u32 scs;
u32 scs_set;
struct fuse_bank {
u32 fuse_regs[0x20];
struct fuse_bank {
u32 fuse_regs[0x20];
};
struct fuse_bank4_regs {
};
struct fuse_bank4_regs {
u32 mac_addr_low;
u32 rsvd2[3];
u32 mac_addr_high;
u32 mac_addr_low;
u32 rsvd2[3];
u32 mac_addr_high;
+ u32 rsvd3[0xb];
+ u32 gp1;
+ u32 rsvd4[7];
* i.MX6Q ARD RevB: 0x02
*/
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
* i.MX6Q ARD RevB: 0x02
*/
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
- int reg = readl(&ocotp->gp1);
+ struct fuse_bank *bank = &ocotp->bank[4];
+ struct fuse_bank4_regs *fuse =
+ (struct fuse_bank4_regs *)bank->fuse_regs;
+ int reg = readl(&fuse->gp1);
int ret;
switch (reg >> 8 & 0x0F) {
int ret;
switch (reg >> 8 & 0x0F) {