+#define BARRIER_TEST_PATTERN (0xdeadbeef)
+
+void lpfc_reset_barrier(struct lpfc_hba * phba)
+{
+ uint32_t * resp_buf;
+ uint32_t * mbox_buf;
+ volatile uint32_t mbox;
+ uint32_t hc_copy;
+ int i;
+ uint8_t hdrtype;
+
+ pci_read_config_byte(phba->pcidev, PCI_HEADER_TYPE, &hdrtype);
+ if (hdrtype != 0x80 ||
+ (FC_JEDEC_ID(phba->vpd.rev.biuRev) != HELIOS_JEDEC_ID &&
+ FC_JEDEC_ID(phba->vpd.rev.biuRev) != THOR_JEDEC_ID))
+ return;
+
+ /*
+ * Tell the other part of the chip to suspend temporarily all
+ * its DMA activity.
+ */
+ resp_buf = (uint32_t *)phba->MBslimaddr;
+
+ /* Disable the error attention */
+ hc_copy = readl(phba->HCregaddr);
+ writel((hc_copy & ~HC_ERINT_ENA), phba->HCregaddr);
+ readl(phba->HCregaddr); /* flush */
+
+ if (readl(phba->HAregaddr) & HA_ERATT) {
+ /* Clear Chip error bit */
+ writel(HA_ERATT, phba->HAregaddr);
+ phba->stopped = 1;
+ }
+
+ mbox = 0;
+ ((MAILBOX_t *)&mbox)->mbxCommand = MBX_KILL_BOARD;
+ ((MAILBOX_t *)&mbox)->mbxOwner = OWN_CHIP;
+
+ writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
+ mbox_buf = (uint32_t *)phba->MBslimaddr;
+ writel(mbox, mbox_buf);
+
+ for (i = 0;
+ readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN) && i < 50; i++)
+ mdelay(1);
+
+ if (readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN)) {
+ if (phba->sli.sli_flag & LPFC_SLI2_ACTIVE ||
+ phba->stopped)
+ goto restore_hc;
+ else
+ goto clear_errat;
+ }
+
+ ((MAILBOX_t *)&mbox)->mbxOwner = OWN_HOST;
+ for (i = 0; readl(resp_buf) != mbox && i < 500; i++)
+ mdelay(1);
+
+clear_errat:
+
+ while (!(readl(phba->HAregaddr) & HA_ERATT) && ++i < 500)
+ mdelay(1);
+
+ if (readl(phba->HAregaddr) & HA_ERATT) {
+ writel(HA_ERATT, phba->HAregaddr);
+ phba->stopped = 1;
+ }
+
+restore_hc:
+ writel(hc_copy, phba->HCregaddr);
+ readl(phba->HCregaddr); /* flush */
+}
+