This saves stack and code memory for local copy, and
consumes initialized data memory. For 22 of the 29
kirkwood-based boards, this results in a global saving
of about 30 bytes. For 7 of them, it results in an
increase of 6 to 14 bytes.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
19 files changed:
#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
#define MPP_NR_REGS (1 + MPP_MAX/8)
#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4))
#define MPP_NR_REGS (1 + MPP_MAX/8)
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
{
u32 mpp_ctrl[MPP_NR_REGS];
unsigned int variant_mask;
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn, /* SPI Flash */
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP0_SPI_SCn, /* SPI Flash */
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
RD6281A_OE_LOW, RD6281A_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
RD6281A_OE_LOW, RD6281A_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
* Multi-Purpose Pins Functionality configuration
* These strappings are taken from the original vendor uboot port.
*/
* Multi-Purpose Pins Functionality configuration
* These strappings are taken from the original vendor uboot port.
*/
+ static const u32 kwmpp_config[] = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
DNS325_OE_LOW, DNS325_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
DNS325_OE_LOW, DNS325_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
TK71_OE_LOW, TK71_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
TK71_OE_LOW, TK71_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
#define MASK_RBI_DEFECT_16 0x01
/* Multi-Purpose Pins Functionality configuration */
#define MASK_RBI_DEFECT_16 0x01
/* Multi-Purpose Pins Functionality configuration */
+static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
/* Set SATA activity LEDs to default off */
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
/* Multi-Purpose Pins Functionality configuration */
/* Set SATA activity LEDs to default off */
writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
/* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
{
struct spi_slave *slave;
u32 data;
{
struct spi_slave *slave;
u32 data;
- u32 kwspi_mpp_config[] = { 0, 0 };
+ static const u32 kwspi_mpp_config[2][2] = {
+ { MPP0_SPI_SCn, 0 }, /* if cs == 0 */
+ { MPP7_SPI_SCn, 0 } /* if cs != 0 */
+ };
if (!spi_cs_is_valid(bus, cs))
return NULL;
if (!spi_cs_is_valid(bus, cs))
return NULL;
writel(KWSPI_IRQMASK, &spireg->irq_mask);
/* program mpp registers to select SPI_CSn */
writel(KWSPI_IRQMASK, &spireg->irq_mask);
/* program mpp registers to select SPI_CSn */
- if (cs) {
- kwspi_mpp_config[0] = MPP7_SPI_SCn;
- } else {
- kwspi_mpp_config[0] = MPP0_SPI_SCn;
- }
- kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back);
+ kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);