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inline | side by side (from parent 1:
cfa7fd7)
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Setup an Address Translation Entry as specified. Use either the Bridge
* internal maps or the external map RAM, as appropriate.
*/
* Setup an Address Translation Entry as specified. Use either the Bridge
* internal maps or the external map RAM, as appropriate.
*/
-static inline u64 *pcibr_ate_addr(struct pcibus_info *pcibus_info,
+static inline u64 __iomem *pcibr_ate_addr(struct pcibus_info *pcibus_info,
int ate_index)
{
if (ate_index < pcibus_info->pbi_int_ate_size) {
int ate_index)
{
if (ate_index < pcibus_info->pbi_int_ate_size) {
-tioce_mmr_war_pre(struct tioce_kernel *kern, void *mmr_addr)
+tioce_mmr_war_pre(struct tioce_kernel *kern, void __iomem *mmr_addr)
{
u64 mmr_base;
u64 mmr_offset;
{
u64 mmr_base;
u64 mmr_offset;
return;
mmr_base = kern->ce_common->ce_pcibus.bs_base;
return;
mmr_base = kern->ce_common->ce_pcibus.bs_base;
- mmr_offset = (u64)mmr_addr - mmr_base;
+ mmr_offset = (unsigned long)mmr_addr - mmr_base;
if (mmr_offset < 0x45000) {
u64 mmr_war_offset;
if (mmr_offset < 0x45000) {
u64 mmr_war_offset;
-tioce_mmr_war_post(struct tioce_kernel *kern, void *mmr_addr)
+tioce_mmr_war_post(struct tioce_kernel *kern, void __iomem *mmr_addr)
{
u64 mmr_base;
u64 mmr_offset;
{
u64 mmr_base;
u64 mmr_offset;
return;
mmr_base = kern->ce_common->ce_pcibus.bs_base;
return;
mmr_base = kern->ce_common->ce_pcibus.bs_base;
- mmr_offset = (u64)mmr_addr - mmr_base;
+ mmr_offset = (unsigned long)mmr_addr - mmr_base;
if (mmr_offset < 0x45000) {
if (mmr_offset == 0x100)
if (mmr_offset < 0x45000) {
if (mmr_offset == 0x100)
* @pci_dev.
*/
static inline void
* @pci_dev.
*/
static inline void
-pcidev_to_tioce(struct pci_dev *pdev, struct tioce **base,
+pcidev_to_tioce(struct pci_dev *pdev, struct tioce __iomem **base,
struct tioce_kernel **kernel, int *port)
{
struct pcidev_info *pcidev_info;
struct tioce_kernel **kernel, int *port)
{
struct pcidev_info *pcidev_info;
ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
if (base)
ce_kernel = (struct tioce_kernel *)ce_common->ce_kernel_private;
if (base)
- *base = (struct tioce *)ce_common->ce_pcibus.bs_base;
+ *base = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
if (kernel)
*kernel = ce_kernel;
if (kernel)
*kernel = ce_kernel;
u64 pagesize;
int msi_capable, msi_wanted;
u64 *ate_shadow;
u64 pagesize;
int msi_capable, msi_wanted;
u64 *ate_shadow;
+ struct tioce __iomem *ce_mmr;
u64 bus_base;
struct tioce_dmamap *map;
u64 bus_base;
struct tioce_dmamap *map;
- ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
+ ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
switch (type) {
case TIOCE_ATE_M32:
switch (type) {
case TIOCE_ATE_M32:
+ struct tioce __iomem *ce_mmr;
struct tioce_kernel *ce_kern;
u64 ct_upper;
u64 ct_lower;
struct tioce_kernel *ce_kern;
u64 ct_upper;
u64 ct_lower;
int i;
int port;
struct tioce_kernel *ce_kern;
int i;
int port;
struct tioce_kernel *ce_kern;
+ struct tioce __iomem *ce_mmr;
unsigned long flags;
bus_addr = tioce_dma_barrier(bus_addr, 0);
unsigned long flags;
bus_addr = tioce_dma_barrier(bus_addr, 0);
tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
{
int ate_index, last_ate, ps;
tioce_reserve_m32(struct tioce_kernel *ce_kern, u64 base, u64 limit)
{
int ate_index, last_ate, ps;
+ struct tioce __iomem *ce_mmr;
- ce_mmr = (struct tioce *)ce_kern->ce_common->ce_pcibus.bs_base;
+ ce_mmr = (struct tioce __iomem *)ce_kern->ce_common->ce_pcibus.bs_base;
ps = ce_kern->ce_ate3240_pagesize;
ate_index = ATE_PAGE(base, ps);
last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
ps = ce_kern->ce_ate3240_pagesize;
ate_index = ATE_PAGE(base, ps);
last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1;
int dev;
u32 tmp;
unsigned int seg, bus;
int dev;
u32 tmp;
unsigned int seg, bus;
- struct tioce *tioce_mmr;
+ struct tioce __iomem *tioce_mmr;
struct tioce_kernel *tioce_kern;
tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
struct tioce_kernel *tioce_kern;
tioce_kern = kzalloc(sizeof(struct tioce_kernel), GFP_KERNEL);
- tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
+ tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
CE_URE_PAGESIZE_MASK);
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
tioce_mmr_clri(tioce_kern, &tioce_mmr->ce_ure_page_map,
CE_URE_PAGESIZE_MASK);
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_ure_page_map,
struct pcidev_info *pcidev_info;
struct tioce_common *ce_common;
struct tioce_kernel *ce_kern;
struct pcidev_info *pcidev_info;
struct tioce_common *ce_common;
struct tioce_kernel *ce_kern;
+ struct tioce __iomem *ce_mmr;
u64 force_int_val;
if (!sn_irq_info->irq_bridge)
u64 force_int_val;
if (!sn_irq_info->irq_bridge)
return;
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
return;
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
- ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
+ ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
/*
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
/*
struct pcidev_info *pcidev_info;
struct tioce_common *ce_common;
struct tioce_kernel *ce_kern;
struct pcidev_info *pcidev_info;
struct tioce_common *ce_common;
struct tioce_kernel *ce_kern;
+ struct tioce __iomem *ce_mmr;
return;
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
return;
ce_common = (struct tioce_common *)pcidev_info->pdi_pcibus_info;
- ce_mmr = (struct tioce *)ce_common->ce_pcibus.bs_base;
+ ce_mmr = (struct tioce __iomem *)ce_common->ce_pcibus.bs_base;
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
bit = sn_irq_info->irq_int_bit;
ce_kern = (struct tioce_kernel *)ce_common->ce_kernel_private;
bit = sn_irq_info->irq_int_bit;
cnodeid_t my_cnode, mem_cnode;
struct tioce_common *tioce_common;
struct tioce_kernel *tioce_kern;
cnodeid_t my_cnode, mem_cnode;
struct tioce_common *tioce_common;
struct tioce_kernel *tioce_kern;
- struct tioce *tioce_mmr;
+ struct tioce __iomem *tioce_mmr;
/*
* Allocate kernel bus soft and copy from prom.
/*
* Allocate kernel bus soft and copy from prom.
- tioce_mmr = (struct tioce *)tioce_common->ce_pcibus.bs_base;
+ tioce_mmr = (struct tioce __iomem *)tioce_common->ce_pcibus.bs_base;
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
~0ULL);
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_int_status_alias, ~0ULL);
tioce_mmr_seti(tioce_kern, &tioce_mmr->ce_adm_error_summary_alias,
~0ULL);
extern void pcireg_force_intr_set(struct pcibus_info *, int);
extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
extern void pcireg_force_intr_set(struct pcibus_info *, int);
extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
-extern u64 * pcireg_int_ate_addr(struct pcibus_info *, int);
+extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
extern int pcibr_ate_alloc(struct pcibus_info *, int);
extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
extern int pcibr_ate_alloc(struct pcibus_info *, int);
tioca_tlbflush(struct tioca_kernel *tioca_kernel)
{
volatile u64 tmp;
tioca_tlbflush(struct tioca_kernel *tioca_kernel)
{
volatile u64 tmp;
- volatile struct tioca *ca_base;
+ volatile struct tioca __iomem *ca_base;
struct tioca_common *tioca_common;
tioca_common = tioca_kernel->ca_common;
struct tioca_common *tioca_common;
tioca_common = tioca_kernel->ca_common;
- ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
+ ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
/*
* Explicit flushes not needed if GART is in cached mode
/*
* Explicit flushes not needed if GART is in cached mode
u64 ct_start; /* coretalk start address */
u64 pci_start; /* bus start address */
u64 ct_start; /* coretalk start address */
u64 pci_start; /* bus start address */
- u64 *ate_hw; /* hw ptr of first ate in map */
+ u64 __iomem *ate_hw;/* hw ptr of first ate in map */
u64 *ate_shadow; /* shadow ptr of firat ate */
u16 ate_count; /* # ate's in the map */
};
u64 *ate_shadow; /* shadow ptr of firat ate */
u16 ate_count; /* # ate's in the map */
};