+ }
+
+ /* NOTE: vendors didn't always make the same implementation
+ * choices for RHSC. Sometimes it triggers on an edge (like
+ * setting and maybe clearing a port status change bit); and
+ * it's level-triggered on other silicon, active until khubd
+ * clears all active port status change bits. Poll by timer
+ * til it's fully debounced and the difference won't matter.
+ */
+ if (ints & OHCI_INTR_RHSC) {
+ ohci_vdbg (ohci, "rhsc\n");
+ ohci_writel (ohci, OHCI_INTR_RHSC, ®s->intrdisable);
+ hcd->poll_rh = 1;
+ ohci->next_statechange = jiffies + STATECHANGE_DELAY;
+ ohci_writel (ohci, OHCI_INTR_RHSC, ®s->intrstatus);
+ usb_hcd_poll_rh_status(hcd);
+ }