drm/i915: Only flush fbc on sw when fbc is enabled.

Avoid touching fbc register when fbc is disabled.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 675e8a2ce988faaef92ca835b980e713a8fd60a0..6f3b94b7300bf36445520f2184314c8256f34c8d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -352,6 +352,9 @@ void gen8_fbc_sw_flush(struct drm_device *dev, u32 value)
        if (!IS_GEN8(dev))
                return;
 
+       if (!intel_fbc_enabled(dev))
+               return;
+
        I915_WRITE(MSG_FBC_REND_STATE, value);
 }