Merge remote-tracking branch 'drm/drm-next'

Conflicts:
	drivers/gpu/drm/i915/i915_gem.c
	drivers/gpu/drm/i915/i915_gem_execbuffer.c
	drivers/gpu/drm/i915/i915_gem_gtt.c

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/gpu/drm/i915/i915_dma.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.h
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem.c
index 3326770c9ed2618d914d931a8fd5b54b2137c02b,e1fa919017e2e6dfe84a924a40828f19a5d52f45..ca1b84916537c546b8806c9460d690afc63a438e
--- 1/drivers/gpu/drm/i915/i915_gem.c
--- 2/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@@ -43,7 -43,14 +43,9 @@@ static void i915_gem_object_flush_cpu_w
  static __must_check int
  i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
                               bool readonly);
+ static void
+ i915_gem_object_retire(struct drm_i915_gem_object *obj);
  
 -static int i915_gem_phys_pwrite(struct drm_device *dev,
 -                              struct drm_i915_gem_object *obj,
 -                              struct drm_i915_gem_pwrite *args,
 -                              struct drm_file *file);
 -
  static void i915_gem_write_fence(struct drm_device *dev, int reg,
                                 struct drm_i915_gem_object *obj);
  static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,

diff --cc drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 20fef6c502676b2c82bdd19cbe343f5f864b0ccc,47fe8ecef135faacd0967805e213f23e764e4f1b..8a07ae899ef1fd07cbbd0483723e1ee291a3c22a
--- 1/drivers/gpu/drm/i915/i915_gem_execbuffer.c
--- 2/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@@ -1018,25 -1007,37 +1026,56 @@@ i915_reset_gen7_sol_offsets(struct drm_
        return 0;
  }
  
 +static struct drm_i915_gem_object *
 +eb_get_batch(struct eb_vmas *eb)
 +{
 +      struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
 +
 +      /*
 +       * SNA is doing fancy tricks with compressing batch buffers, which leads
 +       * to negative relocation deltas. Usually that works out ok since the
 +       * relocate address is still positive, except when the batch is placed
 +       * very low in the GTT. Ensure this doesn't happen.
 +       *
 +       * Note that actual hangs have only been observed on gen7, but for
 +       * paranoia do it everywhere.
 +       */
 +      vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 +
 +      return vma->obj;
 +}
 +
+ /**
+  * Find one BSD ring to dispatch the corresponding BSD command.
+  * The Ring ID is returned.
+  */
+ static int gen8_dispatch_bsd_ring(struct drm_device *dev,
+                                 struct drm_file *file)
+ {
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct drm_i915_file_private *file_priv = file->driver_priv;
+ 
+       /* Check whether the file_priv is using one ring */
+       if (file_priv->bsd_ring)
+               return file_priv->bsd_ring->id;
+       else {
+               /* If no, use the ping-pong mechanism to select one ring */
+               int ring_id;
+ 
+               mutex_lock(&dev->struct_mutex);
+               if (dev_priv->ring_index == 0) {
+                       ring_id = VCS;
+                       dev_priv->ring_index = 1;
+               } else {
+                       ring_id = VCS2;
+                       dev_priv->ring_index = 0;
+               }
+               file_priv->bsd_ring = &dev_priv->ring[ring_id];
+               mutex_unlock(&dev->struct_mutex);
+               return ring_id;
+       }
+ }
+ 
  static int
  i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                       struct drm_file *file,

diff --cc drivers/gpu/drm/i915/i915_gem_gtt.c
index 5deb22864c522a6513de4c49742e725eef987d9b,496916298e8a59ef89323e53a97a1beae44d909b..4dcc0e5ab30c525e741f6506f6453e0330fb93ec
--- 1/drivers/gpu/drm/i915/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -62,62 -48,13 +62,9 @@@ static int sanitize_enable_ppgtt(struc
        }
  #endif
  
 -      /* Full ppgtt disabled by default for now due to issues. */
 -      if (full)
 -              return HAS_PPGTT(dev) && (i915.enable_ppgtt == 2);
 -      else
 -              return HAS_ALIASING_PPGTT(dev);
 +      return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
  }
  
- #define GEN6_PPGTT_PD_ENTRIES 512
- #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
- typedef uint64_t gen8_gtt_pte_t;
- typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
- 
- /* PPGTT stuff */
- #define GEN6_GTT_ADDR_ENCODE(addr)    ((addr) | (((addr) >> 28) & 0xff0))
- #define HSW_GTT_ADDR_ENCODE(addr)     ((addr) | (((addr) >> 28) & 0x7f0))
- 
- #define GEN6_PDE_VALID                        (1 << 0)
- /* gen6+ has bit 11-4 for physical addr bit 39-32 */
- #define GEN6_PDE_ADDR_ENCODE(addr)    GEN6_GTT_ADDR_ENCODE(addr)
- 
- #define GEN6_PTE_VALID                        (1 << 0)
- #define GEN6_PTE_UNCACHED             (1 << 1)
- #define HSW_PTE_UNCACHED              (0)
- #define GEN6_PTE_CACHE_LLC            (2 << 1)
- #define GEN7_PTE_CACHE_L3_LLC         (3 << 1)
- #define GEN6_PTE_ADDR_ENCODE(addr)    GEN6_GTT_ADDR_ENCODE(addr)
- #define HSW_PTE_ADDR_ENCODE(addr)     HSW_GTT_ADDR_ENCODE(addr)
- 
- /* Cacheability Control is a 4-bit value. The low three bits are stored in *
-  * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
-  */
- #define HSW_CACHEABILITY_CONTROL(bits)        ((((bits) & 0x7) << 1) | \
-                                        (((bits) & 0x8) << (11 - 3)))
- #define HSW_WB_LLC_AGE3                       HSW_CACHEABILITY_CONTROL(0x2)
- #define HSW_WB_LLC_AGE0                       HSW_CACHEABILITY_CONTROL(0x3)
- #define HSW_WB_ELLC_LLC_AGE0          HSW_CACHEABILITY_CONTROL(0xb)
- #define HSW_WB_ELLC_LLC_AGE3          HSW_CACHEABILITY_CONTROL(0x8)
- #define HSW_WT_ELLC_LLC_AGE0          HSW_CACHEABILITY_CONTROL(0x6)
- #define HSW_WT_ELLC_LLC_AGE3          HSW_CACHEABILITY_CONTROL(0x7)
- 
- #define GEN8_PTES_PER_PAGE            (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
- #define GEN8_PDES_PER_PAGE            (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
- 
- /* GEN8 legacy style addressis defined as a 3 level page table:
-  * 31:30 | 29:21 | 20:12 |  11:0
-  * PDPE  |  PDE  |  PTE  | offset
-  * The difference as compared to normal x86 3 level page table is the PDPEs are
-  * programmed via register.
-  */
- #define GEN8_PDPE_SHIFT                       30
- #define GEN8_PDPE_MASK                        0x3
- #define GEN8_PDE_SHIFT                        21
- #define GEN8_PDE_MASK                 0x1ff
- #define GEN8_PTE_SHIFT                        12
- #define GEN8_PTE_MASK                 0x1ff
- 
- #define PPAT_UNCACHED_INDEX           (_PAGE_PWT | _PAGE_PCD)
- #define PPAT_CACHED_PDE_INDEX         0 /* WB LLC */
- #define PPAT_CACHED_INDEX             _PAGE_PAT /* WB LLCeLLC */
- #define PPAT_DISPLAY_ELLC_INDEX               _PAGE_PCD /* WT eLLC */
  
  static void ppgtt_bind_vma(struct i915_vma *vma,
                           enum i915_cache_level cache_level,
@@@ -2043,15 -1971,11 +1983,20 @@@ int i915_gem_gtt_init(struct drm_devic
                 gtt->base.total >> 20);
        DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
        DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
 +      /*
 +       * i915.enable_ppgtt is read-only, so do an early pass to validate the
 +       * user's requested state against the hardware/driver capabilities.  We
 +       * do this now so that we can print out any log messages once rather
 +       * than every time we check intel_enable_ppgtt().
 +       */
 +      i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
 +      DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 +
+ #ifdef CONFIG_INTEL_IOMMU
+       if (intel_iommu_gfx_mapped)
+               DRM_INFO("VT-d active for gfx access\n");
+ #endif
+ 
        return 0;
  }
  

diff --cc drivers/gpu/drm/i915/intel_bios.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_panel.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_uncore.c
Simple merge

diff --cc drivers/gpu/drm/radeon/radeon_device.c
Simple merge

diff --cc drivers/staging/imx-drm/imx-drm-core.c
Simple merge

diff --cc drivers/staging/imx-drm/imx-tve.c
Simple merge

diff --cc include/drm/i915_pciids.h
Simple merge

diff --cc lib/Kconfig.debug
Simple merge

diff --cc lib/Makefile
Simple merge