const struct imx_caam_data imx6q_imx_caam_data __initconst = {
.iobase_caam = MXC_CAAM_BASE_ADDR,
+ .iobase_caam_sm = CAAM_SECMEM_BASE_ADDR,
+ .iobase_snvs = MX6Q_SNVS_BASE_ADDR,
.irq_sec_vio = MXC_INT_SNVS_SEC,
.irq_snvs = MX6Q_INT_SNVS,
.jr[0].offset_jr = 0x1000,
.start = data->iobase_caam,
.end = data->iobase_caam + SZ_64K - 1,
.flags = IORESOURCE_MEM,
+ }, {
+ /* Define range for secure memory */
+ .name = "iobase_caam_sm",
+ .start = data->iobase_caam_sm,
+ .end = data->iobase_caam_sm + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ /* Define range for SNVS */
+ .name = "iobase_snvs",
+ .start = data->iobase_snvs,
+ .end = data->iobase_snvs + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
}, {
/* Define interrupt for security violations */
.name = "irq_sec_vio",
};
struct imx_caam_data {
- resource_size_t iobase_caam;
- resource_size_t irq_sec_vio;
- resource_size_t irq_snvs;
+ resource_size_t iobase_caam; /* entirety of CAAM register map */
+ resource_size_t iobase_caam_sm; /* base of secure memory */
+ resource_size_t iobase_snvs; /* base of SNVS */
+ resource_size_t irq_sec_vio; /* SNVS security violation */
+ resource_size_t irq_snvs; /* SNVS consolidated (incl. RTC) */
struct imx_caam_jr_data jr[4]; /* offset+IRQ for each possible ring */
};
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
-#define CAAM_ARB_BASE_ADDR 0x00100000
-#define CAAM_ARB_END_ADDR 0x00103FFF
+#define CAAM_SECMEM_BASE_ADDR 0x00100000
+#define CAAM_SECMEM_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
#define APBH_DMA_ARB_END_ADDR 0x00117FFF
#define MX6Q_HDMI_ARB_BASE_ADDR 0x00120000