struct hdmi_pll_data {
void __iomem *base;
+ struct hdmi_wp_data *wp;
+
struct hdmi_pll_info info;
};
int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
/* HDMI PLL funcs */
-int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
-void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
+int hdmi_pll_enable(struct hdmi_pll_data *pll);
+void hdmi_pll_disable(struct hdmi_pll_data *pll);
void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin,
unsigned long target_tmds);
-int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
+int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
+ struct hdmi_wp_data *wp);
/* HDMI PHY funcs */
int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);
/* config the PLL and PHY hdmi_set_pll_pwrfirst */
- r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
+ r = hdmi_pll_enable(&hdmi.pll);
if (r) {
DSSDBG("Failed to lock PLL\n");
goto err_pll_enable;
err_phy_cfg:
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
- hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
+ hdmi_pll_disable(&hdmi.pll);
err_pll_enable:
hdmi_power_off_core(dssdev);
return -EIO;
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
- hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
+ hdmi_pll_disable(&hdmi.pll);
hdmi_power_off_core(dssdev);
}
if (r)
return r;
- r = hdmi_pll_init(pdev, &hdmi.pll);
+ r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
if (r)
return r;
hdmi_wp_get_irqstatus(&hdmi.wp));
/* config the PLL and PHY hdmi_set_pll_pwrfirst */
- r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
+ r = hdmi_pll_enable(&hdmi.pll);
if (r) {
DSSDBG("Failed to lock PLL\n");
goto err_pll_enable;
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
err_phy_pwr:
err_phy_cfg:
- hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
+ hdmi_pll_disable(&hdmi.pll);
err_pll_enable:
hdmi_power_off_core(dssdev);
return -EIO;
hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
- hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
+ hdmi_pll_disable(&hdmi.pll);
hdmi_power_off_core(dssdev);
}
if (r)
return r;
- r = hdmi_pll_init(pdev, &hdmi.pll);
+ r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
if (r)
return r;
return 0;
}
-int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
+int hdmi_pll_enable(struct hdmi_pll_data *pll)
{
+ struct hdmi_wp_data *wp = pll->wp;
u16 r = 0;
r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
return 0;
}
-void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
+void hdmi_pll_disable(struct hdmi_pll_data *pll)
{
+ struct hdmi_wp_data *wp = pll->wp;
+
hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
}
return 0;
}
-int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
+int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
+ struct hdmi_wp_data *wp)
{
int r;
struct resource *res;
+ pll->wp = wp;
+
r = hdmi_pll_init_features(pdev);
if (r)
return r;