]> git.karo-electronics.de Git - mv-sheeva.git/commitdiff
Merge branch 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git...
authorArnd Bergmann <arnd@arndb.de>
Wed, 29 Feb 2012 20:53:57 +0000 (20:53 +0000)
committerArnd Bergmann <arnd@arndb.de>
Wed, 29 Feb 2012 20:53:57 +0000 (20:53 +0000)
* 'fixes-non-critical' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  OMAP4: dma: Correct CPU version check for dma_common_ch_end
  ARM: OMAP: Fix section mismatch warning for platform_cpu_die()
  ARM: OMAP: fix section mismatch warning for omap4_hotplug_cpu()
  ARM: OMAP: convert omap_device_build() and callers to __init
  ARM: OMAP2+: Mark omap_hsmmc_init and omap_mux related functions as __init
  ARM: OMAP2+: Fix multiple randconfig errors with SOC_OMAP and SOC_OMAP_NOOP
  ARM: OMAP: Fix devexit for dma when CONFIG_HOTPLUG is not set
  ARM: OMAP2+: Fix devexit for smartreflex when CONFIG_HOTPLUG is not set
  ARM: OMAP2+: Fix zoom LCD backlight if TWL_CORE is not selected
  ARM: OMAP2+: Fix board_mux section type conflict when OMAP_MUX is not set
  ARM: OMAP2+: Fix OMAP_HDQ_BASE build error
  ARM: OMAP2+: Fix Kconfig dependencies for USB_ARCH_HAS_EHCI
  ARM: OMAP2+: I2C: always compile I2C reset code, even if I2C driver is not built
  ARM: OMAP2+: Split omap2_hsmmc_init() to properly support I2C GPIO pins
  ARM: OMAP: omap_device: Expose omap_device_{alloc, delete, register}
  ARM: OMAP: Fix build error when mmc_omap is built as module
  ARM: OMAP: Fix kernel panic with HSMMC when twl4030_gpio is a module

12 files changed:
arch/arm/configs/imx_v4_v5_defconfig
arch/arm/configs/lpc32xx_defconfig [new file with mode: 0644]
arch/arm/mach-davinci/dma.c
arch/arm/mach-davinci/include/mach/edma.h
arch/arm/mach-imx/mach-pcm038.c
arch/arm/mach-imx/mm-imx3.c
arch/arm/mach-lpc32xx/clock.c
arch/arm/mach-lpc32xx/common.h
arch/arm/mach-lpc32xx/include/mach/platform.h
arch/arm/mach-lpc32xx/phy3250.c
arch/arm/mach-lpc32xx/pm.c
arch/arm/mach-lpc32xx/timer.c

index a22e93079063855cc5bf8047864bda8284a5ec01..d88fb87b414d721f9359252798efdd680070e1d7 100644 (file)
@@ -68,6 +68,7 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
new file mode 100644 (file)
index 0000000..fb20881
--- /dev/null
@@ -0,0 +1,145 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_LPC32XX=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
+CONFIG_CPU_IDLE=y
+CONFIG_FPE_NWFPE=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_AOUT=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_MUSEUM_IDS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_PHYLIB=y
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_LPC32XX=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PNX=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_PNX4008_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_SOC=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_LPC32XX=y
+CONFIG_EXT2_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
index da90103a313dc2a7d3b2e7e2f5e99d418cbd02d2..fd33919c95d4ef4a1ae9c7ad3437f52526713730 100644 (file)
@@ -1508,12 +1508,8 @@ static int __init edma_probe(struct platform_device *pdev)
                        goto fail;
                }
 
-               /* Everything lives on transfer controller 1 until otherwise
-                * specified. This way, long transfers on the low priority queue
-                * started by the codec engine will not cause audio defects.
-                */
                for (i = 0; i < edma_cc[j]->num_channels; i++)
-                       map_dmach_queue(j, i, EVENTQ_1);
+                       map_dmach_queue(j, i, info[j]->default_queue);
 
                queue_tc_mapping = info[j]->queue_tc_mapping;
                queue_priority_mapping = info[j]->queue_priority_mapping;
index 20c77f29bf0f3a74c36ca48eb16085d0e87abacb..7e84c906ceff4046aef96e484d9bc0b5dd895711 100644 (file)
@@ -250,6 +250,11 @@ struct edma_soc_info {
        unsigned        n_slot;
        unsigned        n_tc;
        unsigned        n_cc;
+       /*
+        * Default queue is expected to be a low-priority queue.
+        * This way, long transfers on the default queue started
+        * by the codec engine will not cause audio defects.
+        */
        enum dma_event_q        default_queue;
 
        /* Resource reservation for other cores */
index 16f126da9f8f543abf7d175477778b5636bb0a55..2f3debe2a11335f60de6f2913cb4ba9452127567 100644 (file)
@@ -233,7 +233,7 @@ static struct regulator_init_data sdhc1_data = {
 
 static struct regulator_consumer_supply cam_consumers[] = {
        {
-               .dev    = NULL,
+               .dev_name = NULL,
                .supply = "imx_cam_vcc",
        },
 };
index 31807d2a8b7bf1a65d57c8f4cb748bb9e6697934..8a31e6f5d66a6567ecb089f1373261ac87abcbf3 100644 (file)
@@ -78,7 +78,7 @@ static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
        return __arm_ioremap(phys_addr, size, mtype);
 }
 
-void imx3_init_l2x0(void)
+void __init imx3_init_l2x0(void)
 {
        void __iomem *l2x0_base;
        void __iomem *clkctl_base;
index 1e027514096d0d9e15f87152a0e92761f1e959e8..0e01bf44479c27a4f45ba037848354845e0aa8d3 100644 (file)
@@ -82,6 +82,7 @@
  *   will also impact the individual peripheral rates.
  */
 
+#include <linux/export.h>
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/errno.h>
 #include "clock.h"
 #include "common.h"
 
+static DEFINE_SPINLOCK(global_clkregs_lock);
+
 static struct clk clk_armpll;
 static struct clk clk_usbpll;
-static DEFINE_MUTEX(clkm_lock);
 
 /*
  * Post divider values for PLLs based on selected register value
@@ -127,7 +129,7 @@ static struct clk osc_32KHz = {
 static int local_pll397_enable(struct clk *clk, int enable)
 {
        u32 reg;
-       unsigned long timeout = 1 + msecs_to_jiffies(10);
+       unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
        reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
 
@@ -142,7 +144,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
                /* Wait for PLL397 lock */
                while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
                        LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
-                       (timeout > jiffies))
+                       time_before(jiffies, timeout))
                        cpu_relax();
 
                if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
@@ -156,7 +158,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
 static int local_oscmain_enable(struct clk *clk, int enable)
 {
        u32 reg;
-       unsigned long timeout = 1 + msecs_to_jiffies(10);
+       unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
        reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
 
@@ -171,7 +173,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
                /* Wait for main oscillator to start */
                while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
                        LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
-                       (timeout > jiffies))
+                       time_before(jiffies, timeout))
                        cpu_relax();
 
                if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
@@ -383,7 +385,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
 {
        u32 reg;
        int ret = -ENODEV;
-       unsigned long timeout = 1 + msecs_to_jiffies(10);
+       unsigned long timeout = jiffies + msecs_to_jiffies(10);
 
        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
 
@@ -396,7 +398,7 @@ static int local_usbpll_enable(struct clk *clk, int enable)
                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
 
                /* Wait for PLL lock */
-               while ((timeout > jiffies) & (ret == -ENODEV)) {
+               while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
                        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
                        if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
                                ret = 0;
@@ -891,20 +893,8 @@ static struct clk clk_lcd = {
        .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 };
 
-static inline void clk_lock(void)
-{
-       mutex_lock(&clkm_lock);
-}
-
-static inline void clk_unlock(void)
-{
-       mutex_unlock(&clkm_lock);
-}
-
 static void local_clk_disable(struct clk *clk)
 {
-       WARN_ON(clk->usecount == 0);
-
        /* Don't attempt to disable clock if it has no users */
        if (clk->usecount > 0) {
                clk->usecount--;
@@ -947,10 +937,11 @@ static int local_clk_enable(struct clk *clk)
 int clk_enable(struct clk *clk)
 {
        int ret;
+       unsigned long flags;
 
-       clk_lock();
+       spin_lock_irqsave(&global_clkregs_lock, flags);
        ret = local_clk_enable(clk);
-       clk_unlock();
+       spin_unlock_irqrestore(&global_clkregs_lock, flags);
 
        return ret;
 }
@@ -961,9 +952,11 @@ EXPORT_SYMBOL(clk_enable);
  */
 void clk_disable(struct clk *clk)
 {
-       clk_lock();
+       unsigned long flags;
+
+       spin_lock_irqsave(&global_clkregs_lock, flags);
        local_clk_disable(clk);
-       clk_unlock();
+       spin_unlock_irqrestore(&global_clkregs_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 
@@ -972,13 +965,7 @@ EXPORT_SYMBOL(clk_disable);
  */
 unsigned long clk_get_rate(struct clk *clk)
 {
-       unsigned long rate;
-
-       clk_lock();
-       rate = clk->get_rate(clk);
-       clk_unlock();
-
-       return rate;
+       return clk->get_rate(clk);
 }
 EXPORT_SYMBOL(clk_get_rate);
 
@@ -994,11 +981,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         * the actual rate set as part of the peripheral dividers
         * instead of high level clock control
         */
-       if (clk->set_rate) {
-               clk_lock();
+       if (clk->set_rate)
                ret = clk->set_rate(clk, rate);
-               clk_unlock();
-       }
 
        return ret;
 }
@@ -1009,15 +993,11 @@ EXPORT_SYMBOL(clk_set_rate);
  */
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
-       clk_lock();
-
        if (clk->round_rate)
                rate = clk->round_rate(clk, rate);
        else
                rate = clk->get_rate(clk);
 
-       clk_unlock();
-
        return rate;
 }
 EXPORT_SYMBOL(clk_round_rate);
@@ -1075,10 +1055,10 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
        _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
        _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
-       _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
-       _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
+       _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
+       _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
        _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
-       _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
+       _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
        _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
        _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
        _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
index 4b4e700343c14f89ecefb18af80810d031ba5a2d..75640bfb097fab64de85e38a39a2a50b35db088c 100644 (file)
@@ -65,7 +65,6 @@ extern u32 clk_get_pclk_div(void);
  */
 extern void lpc32xx_get_uid(u32 devid[4]);
 
-extern void lpc32xx_watchdog_reset(void);
 extern u32 lpc32xx_return_iram_size(void);
 
 /*
index 14ea8d1aadb55a577f2b2427ec5e4f05c5d8180f..c584f5bb164fe5d8cedf6bb9cc3d05767c8faac3 100644 (file)
 /*
  * Timer/counter register offsets
  */
-#define LCP32XX_TIMER_IR(x)                    io_p2v((x) + 0x00)
-#define LCP32XX_TIMER_TCR(x)                   io_p2v((x) + 0x04)
-#define LCP32XX_TIMER_TC(x)                    io_p2v((x) + 0x08)
-#define LCP32XX_TIMER_PR(x)                    io_p2v((x) + 0x0C)
-#define LCP32XX_TIMER_PC(x)                    io_p2v((x) + 0x10)
-#define LCP32XX_TIMER_MCR(x)                   io_p2v((x) + 0x14)
-#define LCP32XX_TIMER_MR0(x)                   io_p2v((x) + 0x18)
-#define LCP32XX_TIMER_MR1(x)                   io_p2v((x) + 0x1C)
-#define LCP32XX_TIMER_MR2(x)                   io_p2v((x) + 0x20)
-#define LCP32XX_TIMER_MR3(x)                   io_p2v((x) + 0x24)
-#define LCP32XX_TIMER_CCR(x)                   io_p2v((x) + 0x28)
-#define LCP32XX_TIMER_CR0(x)                   io_p2v((x) + 0x2C)
-#define LCP32XX_TIMER_CR1(x)                   io_p2v((x) + 0x30)
-#define LCP32XX_TIMER_CR2(x)                   io_p2v((x) + 0x34)
-#define LCP32XX_TIMER_CR3(x)                   io_p2v((x) + 0x38)
-#define LCP32XX_TIMER_EMR(x)                   io_p2v((x) + 0x3C)
-#define LCP32XX_TIMER_CTCR(x)                  io_p2v((x) + 0x70)
+#define LPC32XX_TIMER_IR(x)                    io_p2v((x) + 0x00)
+#define LPC32XX_TIMER_TCR(x)                   io_p2v((x) + 0x04)
+#define LPC32XX_TIMER_TC(x)                    io_p2v((x) + 0x08)
+#define LPC32XX_TIMER_PR(x)                    io_p2v((x) + 0x0C)
+#define LPC32XX_TIMER_PC(x)                    io_p2v((x) + 0x10)
+#define LPC32XX_TIMER_MCR(x)                   io_p2v((x) + 0x14)
+#define LPC32XX_TIMER_MR0(x)                   io_p2v((x) + 0x18)
+#define LPC32XX_TIMER_MR1(x)                   io_p2v((x) + 0x1C)
+#define LPC32XX_TIMER_MR2(x)                   io_p2v((x) + 0x20)
+#define LPC32XX_TIMER_MR3(x)                   io_p2v((x) + 0x24)
+#define LPC32XX_TIMER_CCR(x)                   io_p2v((x) + 0x28)
+#define LPC32XX_TIMER_CR0(x)                   io_p2v((x) + 0x2C)
+#define LPC32XX_TIMER_CR1(x)                   io_p2v((x) + 0x30)
+#define LPC32XX_TIMER_CR2(x)                   io_p2v((x) + 0x34)
+#define LPC32XX_TIMER_CR3(x)                   io_p2v((x) + 0x38)
+#define LPC32XX_TIMER_EMR(x)                   io_p2v((x) + 0x3C)
+#define LPC32XX_TIMER_CTCR(x)                  io_p2v((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)         (1 << ((n) & 0x3))
-#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)         (1 << (4 + ((n) & 0x3)))
+#define LPC32XX_TIMER_CNTR_MTCH_BIT(n)         (1 << ((n) & 0x3))
+#define LPC32XX_TIMER_CNTR_CAPT_BIT(n)         (1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_TCR_EN              0x1
-#define LCP32XX_TIMER_CNTR_TCR_RESET           0x2
+#define LPC32XX_TIMER_CNTR_TCR_EN              0x1
+#define LPC32XX_TIMER_CNTR_TCR_RESET           0x2
 
 /*
  * mcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)         (0x1 << ((n) * 3))
-#define LCP32XX_TIMER_CNTR_MCR_RESET(n)                (0x1 << (((n) * 3) + 1))
-#define LCP32XX_TIMER_CNTR_MCR_STOP(n)         (0x1 << (((n) * 3) + 2))
+#define LPC32XX_TIMER_CNTR_MCR_MTCH(n)         (0x1 << ((n) * 3))
+#define LPC32XX_TIMER_CNTR_MCR_RESET(n)                (0x1 << (((n) * 3) + 1))
+#define LPC32XX_TIMER_CNTR_MCR_STOP(n)         (0x1 << (((n) * 3) + 2))
 
 /*
  * Standard UART register offsets
 #define LPC32XX_GPIO_P1_MUX_SET                        _GPREG(0x130)
 #define LPC32XX_GPIO_P1_MUX_CLR                        _GPREG(0x134)
 #define LPC32XX_GPIO_P1_MUX_STATE              _GPREG(0x138)
+#define LPC32XX_GPIO_P2_MUX_SET                        _GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR                        _GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE              _GPREG(0x030)
 
 #endif
index bfee5b4551055b2f7c5e1e68b7b07710361b2db0..945a2f24d5e901dbbbec5f07a4380ead6e4bf23e 100644 (file)
@@ -271,6 +271,8 @@ static struct platform_device lpc32xx_gpio_led_device = {
 };
 
 static struct platform_device *phy3250_devs[] __initdata = {
+       &lpc32xx_rtc_device,
+       &lpc32xx_tsc_device,
        &lpc32xx_i2c0_device,
        &lpc32xx_i2c1_device,
        &lpc32xx_i2c2_device,
index b9c80597b7bf231841e572befd9fb83f1ba53fde..207e81275ff01277331eec126c736c397831a370 100644 (file)
@@ -13,7 +13,7 @@
 /*
  * LPC32XX CPU and system power management
  *
- * The LCP32XX has three CPU modes for controlling system power: run,
+ * The LPC32XX has three CPU modes for controlling system power: run,
  * direct-run, and halt modes. When switching between halt and run modes,
  * the CPU transistions through direct-run mode. For Linux, direct-run
  * mode is not used in normal operation. Halt mode is used when the
index b42c909bbeeb12634394ab4d1fcf1f4a5bb3d9ec..c40667c33161700450f9a93874efe5a30fc0d5a5 100644 (file)
 static int lpc32xx_clkevt_next_event(unsigned long delta,
     struct clock_event_device *dev)
 {
-       __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-               LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-       __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
-       __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-               LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+       __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+               LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+       __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+       __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+               LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 
        return 0;
 }
@@ -58,7 +58,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
                 * disable the timer to wait for the first call to
                 * set_next_event().
                 */
-               __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+               __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
                break;
 
        case CLOCK_EVT_MODE_UNUSED:
@@ -81,8 +81,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
        struct clock_event_device *evt = &lpc32xx_clkevt;
 
        /* Clear match */
-       __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-               LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+       __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+               LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 
        evt->event_handler(evt);
 
@@ -128,14 +128,14 @@ static void __init lpc32xx_timer_init(void)
        clkrate = clkrate / clk_get_pclk_div();
 
        /* Initial timer setup */
-       __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-       __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-               LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
-       __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
-       __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
-               LCP32XX_TIMER_CNTR_MCR_STOP(0) |
-               LCP32XX_TIMER_CNTR_MCR_RESET(0),
-               LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+       __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+       __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+               LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+       __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+       __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
+               LPC32XX_TIMER_CNTR_MCR_STOP(0) |
+               LPC32XX_TIMER_CNTR_MCR_RESET(0),
+               LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 
        /* Setup tick interrupt */
        setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
@@ -151,14 +151,14 @@ static void __init lpc32xx_timer_init(void)
        clockevents_register_device(&lpc32xx_clkevt);
 
        /* Use timer1 as clock source. */
-       __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-               LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-       __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
-       __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
-       __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-               LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-
-       clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
+       __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+               LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+       __raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+       __raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+       __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+               LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+
+       clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
                "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
 }