ENGR00155893 [mx6q]clock: correct set parent function

set periph_clk_sel to derive clock from periph_clk2_clk

Signed-off-by: Tony Lin <tony.lin@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 0ccae284bb07016c774c2f0161de75ecebee96f1..58484407ec3be04943a98090a0b69fd33ddfaea0 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -938,9 +938,12 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
                reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
                __raw_writel(reg, MXC_CCM_CBCDR);
        } else {
-               /* Set the periph_clk2_podf divider to divide by 1. */
                reg = __raw_readl(MXC_CCM_CBCDR);
+               /* Set the periph_clk2_podf divider to divide by 1. */
                reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
+               /* Clear periph_clk_sel to select periph_clk2. */
+               reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
+
                __raw_writel(reg, MXC_CCM_CBCDR);
 
                /* Set the periph_clk2_sel mux. */