#include <mach/viv_gpu.h>
#include <mach/ahci_sata.h>
#include <mach/ipu-v3.h>
+#include <mach/mxc_hdmi.h>
#include <linux/gpio.h>
#include <linux/etherdevice.h>
/* I2C3 */
MX6Q_PAD_GPIO_5__I2C3_SCL,
MX6Q_PAD_GPIO_16__I2C3_SDA,
+
+ /* HDMI */
+ MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE,
+ MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0,
+ MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1,
+
+ /* USBOTG ID pin */
MX6Q_PAD_GPIO_1__USBOTG_ID,
};
static const struct esdhc_platform_data mx6q_sabreauto_sd3_data __initconst = {
.irq = gpio_to_irq(MX6Q_SABREAUTO_CAP_TCH_INT),
.platform_data = &p1003_ts_data,
},
+ {
+ I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
+ },
};
static void imx6q_sabreauto_usbotg_vbus(bool on)
},
};
+static struct fsl_mxc_lcd_platform_data hdmi_data = {
+ .ipu_id = 0,
+ .disp_id = 0,
+ .default_ifmt = IPU_PIX_FMT_RGB24,
+};
+
static struct fsl_mxc_lcd_platform_data lcdif_data = {
.ipu_id = 0,
.disp_id = 0,
i2c_register_board_info(2, mxc_i2c2_board_info,
ARRAY_SIZE(mxc_i2c2_board_info));
+ imx6q_add_mxc_hdmi(&hdmi_data);
+
imx6q_add_anatop_thermal_imx(1, &mx6q_sabreauto_anatop_thermal_data);
imx6q_init_fec();
#define SPIN_DELAY 1000000 /* in nanoseconds */
+#define AUDIO_VIDEO_MIN_CLK_FREQ 650000000
+#define AUDIO_VIDEO_MAX_CLK_FREQ 1300000000
+
#define WAIT(exp, timeout) \
({ \
struct timespec nstimeofday; \
.enable = _clk_pfd_enable,
.disable = _clk_pfd_disable,
.set_rate = pfd_set_rate,
- .get_rate = pfd_get_rate,
.round_rate = pfd_round_rate,
};
return 0;
}
+static unsigned long _clk_audio_video_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
+ return AUDIO_VIDEO_MIN_CLK_FREQ;
+
+ if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
+ return AUDIO_VIDEO_MAX_CLK_FREQ;
+
+ return rate;
+}
+
+
static struct clk pll4_audio_main_clk = {
__INIT_CLK_DEBUG(pll4_audio_main_clk)
.parent = &osc_clk,
.disable = _clk_pll_disable,
.set_rate = _clk_audio_video_set_rate,
.get_rate = _clk_audio_video_get_rate,
+ .round_rate = _clk_audio_video_round_rate,
};
.disable = _clk_pll_disable,
.set_rate = _clk_audio_video_set_rate,
.get_rate = _clk_audio_video_get_rate,
+ .round_rate = _clk_audio_video_round_rate,
};
static struct clk pll6_MLB_main_clk = {
.get_rate = _clk_hsi_tx_get_rate,
};
-static struct clk video_27M_clk = {
- __INIT_CLK_DEBUG(video_27M_clk)
+static struct clk hdmi_clk[] = {
+ {
+ __INIT_CLK_DEBUG(hdmi_isfr_clk)
.id = 0,
- .parent = &pll2_pfd_400M,
+ .parent = &pll3_pfd_540M,
+ .secondary = &hdmi_clk[1],
.enable_reg = MXC_CCM_CCGR2,
.enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
.enable = _clk_enable,
.disable = _clk_disable,
+ },
+ {
+ __INIT_CLK_DEBUG(hdmi_iahb_clk)
+ .id = 1,
+ .parent = &ahb_clk,
+ .enable_reg = MXC_CCM_CCGR2,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
};
static struct clk caam_clk[] = {
_REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk),
_REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
_REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
- _REGISTER_CLOCK(NULL, "video_27M_clk", video_27M_clk),
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
+ _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
+ _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
};
clk_set_rate(&pll4_audio_main_clk, 650000000);
clk_set_rate(&pll5_video_main_clk, 650000000);
+ clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
+
clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
clk_set_rate(&gpu3d_shader_clk, 594000000);
clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk);