drm/i915: Do not read GAMMA_MODE register

Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.

v2: Read GAMMA_MODE register value at init (Matt Roper's comment)

v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
    with other registers (Matt Roper's comment).

v4: Mask GAMMA_MODE register with interesting bits when reading

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1458125837-2576-3-git-send-email-lionel.g.landwerlin@intel.com

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 35b7f62428fc2c03824e83cfe85523d82a51c0f7..16657ebfbb4323de3d791143d0d20ac91640e48d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -121,6 +121,8 @@ static void haswell_load_luts(struct drm_crtc *crtc)
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+       struct intel_crtc_state *intel_crtc_state =
+               to_intel_crtc_state(crtc->state);
        bool reenable_ips = false;
 
        /*
@@ -128,11 +130,12 @@ static void haswell_load_luts(struct drm_crtc *crtc)
         * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
         */
        if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
-           ((I915_READ(GAMMA_MODE(intel_crtc->pipe)) & GAMMA_MODE_MODE_MASK) ==
-            GAMMA_MODE_MODE_SPLIT)) {
+           (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
                hsw_disable_ips(intel_crtc);
                reenable_ips = true;
        }
+
+       intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
        I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
 
        i9xx_load_luts(crtc);

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4e0695dde3d00a7e66b8565e9bdd4649eed6f2a5..a06c656b01fd13f88b291548529311456e1bfd13 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9961,6 +9961,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 
        intel_get_pipe_src_size(crtc, pipe_config);
 
+       pipe_config->gamma_mode =
+               I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
+
        if (INTEL_INFO(dev)->gen >= 9) {
                skl_init_scalers(dev, crtc, pipe_config);
        }

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5d0da2290bbce3e294691d91d4e0f1df1bcc7577..d4945bbb7d04ea6e243b69d89457a724adfeb106 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -578,6 +578,9 @@ struct intel_crtc_state {
                 */
                bool need_postvbl_update;
        } wm;
+
+       /* Gamma mode programmed on the pipe */
+       uint32_t gamma_mode;
 };
 
 struct vlv_wm_state {