*/
#include <linux/module.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <mach/at91cap9.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
-static void at91cap9_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
/* --------------------------------------------------------------------
* AT91CAP9 processor initialization
* -------------------------------------------------------------------- */
static void __init at91cap9_ioremap_registers(void)
{
+ at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
}
static void __init at91cap9_initialize(void)
{
at91_arch_reset = at91cap9_reset;
- pm_power_off = at91cap9_poweroff;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Register GPIO subsystem */
*/
#include <linux/module.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <mach/at91sam9260.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
}
};
-static void at91sam9260_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
/* --------------------------------------------------------------------
* AT91SAM9260 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9260_ioremap_registers(void)
{
+ at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
}
static void __init at91sam9260_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
- pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
*/
#include <linux/module.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <mach/at91sam9261.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
}
};
-static void at91sam9261_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
/* --------------------------------------------------------------------
* AT91SAM9261 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9261_ioremap_registers(void)
{
+ at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
}
static void __init at91sam9261_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
- pm_power_off = at91sam9261_poweroff;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);
*/
#include <linux/module.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <mach/at91sam9263.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
}
};
-static void at91sam9263_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
/* --------------------------------------------------------------------
* AT91SAM9263 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9263_ioremap_registers(void)
{
+ at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
static void __init at91sam9263_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
- pm_power_off = at91sam9263_poweroff;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Register GPIO subsystem */
*/
#include <linux/module.h>
-#include <linux/pm.h>
#include <linux/dma-mapping.h>
#include <asm/irq.h>
#include <mach/at91sam9g45.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
#include <mach/cpu.h>
#include "soc.h"
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}
-static void at91sam9g45_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
/* --------------------------------------------------------------------
* AT91SAM9G45 processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9g45_ioremap_registers(void)
{
+ at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
}
static void __init at91sam9g45_initialize(void)
{
at91_arch_reset = at91sam9g45_reset;
- pm_power_off = at91sam9g45_poweroff;
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
/* Register GPIO subsystem */
*/
#include <linux/module.h>
-#include <linux/pm.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <mach/at91sam9rl.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
}
};
-static void at91sam9rl_poweroff(void)
-{
- at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
-
-
/* --------------------------------------------------------------------
* AT91SAM9RL processor initialization
* -------------------------------------------------------------------- */
static void __init at91sam9rl_ioremap_registers(void)
{
+ at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
}
static void __init at91sam9rl_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
- pm_power_off = at91sam9rl_poweroff;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
/* Register GPIO subsystem */
/* reset */
extern void at91sam9_alt_reset(void);
+/* shutdown */
+extern void at91_ioremap_shdwc(u32 base_addr);
+
/* GPIO */
#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
#ifndef AT91_SHDWC_H
#define AT91_SHDWC_H
-#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_shdwc_base;
+
+#define at91_shdwc_read(field) \
+ __raw_readl(at91_shdwc_base + field)
+
+#define at91_shdwc_write(field, value) \
+ __raw_writel(value, at91_shdwc_base + field);
+#endif
+
+#define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
#define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */
#define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
-#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
+#define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
#define AT91_SHDW_WKMODE0_NONE 0
#define AT91_SHDW_WKMODE0_HIGH 1
#define AT91_SHDW_CPTWK0_(x) ((x) << 4)
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
-#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
+#define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
#define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
(0xfffffd50 - AT91_BASE_SYS) : \
#define AT91CAP9_BASE_PIOB 0xfffff400
#define AT91CAP9_BASE_PIOC 0xfffff600
#define AT91CAP9_BASE_PIOD 0xfffff800
+#define AT91CAP9_BASE_SHDWC 0xfffffd10
#define AT91CAP9_BASE_RTT 0xfffffd20
#define AT91CAP9_BASE_PIT 0xfffffd30
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800
+#define AT91SAM9260_BASE_SHDWC 0xfffffd10
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600
#define AT91SAM9261_BASE_PIOC 0xfffff800
+#define AT91SAM9261_BASE_SHDWC 0xfffffd10
#define AT91SAM9261_BASE_RTT 0xfffffd20
#define AT91SAM9261_BASE_PIT 0xfffffd30
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9263_BASE_PIOC 0xfffff600
#define AT91SAM9263_BASE_PIOD 0xfffff800
#define AT91SAM9263_BASE_PIOE 0xfffffa00
+#define AT91SAM9263_BASE_SHDWC 0xfffffd10
#define AT91SAM9263_BASE_RTT0 0xfffffd20
#define AT91SAM9263_BASE_PIT 0xfffffd30
#define AT91SAM9263_BASE_RTT1 0xfffffd50
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
#define AT91SAM9G45_BASE_PIOC 0xfffff600
#define AT91SAM9G45_BASE_PIOD 0xfffff800
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
+#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
#define AT91SAM9G45_BASE_RTT 0xfffffd20
#define AT91SAM9G45_BASE_PIT 0xfffffd30
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9RL_BASE_PIOB 0xfffff600
#define AT91SAM9RL_BASE_PIOC 0xfffff800
#define AT91SAM9RL_BASE_PIOD 0xfffffa00
+#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
#define AT91SAM9RL_BASE_RTT 0xfffffd20
#define AT91SAM9RL_BASE_PIT 0xfffffd30
/*
* Show the reason for the previous system reset.
*/
-#if defined(AT91_SHDWC)
+#if defined(AT91_RSTC)
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
char *reason, *r2 = reset;
u32 reset_type, wake_type;
+ if (!at91_shdwc_base)
+ return;
+
reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
- wake_type = at91_sys_read(AT91_SHDW_SR);
+ wake_type = at91_shdwc_read(AT91_SHDW_SR);
switch (reset_type) {
case AT91_RSTC_RSTTYP_GENERAL:
}
}
-#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
- /* PCK0..PCK3 must be disabled, or configured to use clk32k */
- for (i = 0; i < 4; i++) {
- u32 css;
+ if (IS_BUILTIN(CONFIG_AT91_PROGRAMMABLE_CLOCKS)) {
+ /* PCK0..PCK3 must be disabled, or configured to use clk32k */
+ for (i = 0; i < 4; i++) {
+ u32 css;
- if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
- continue;
+ if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
+ continue;
- css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
- if (css != AT91_PMC_CSS_SLOW) {
- pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
- return 0;
+ css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
+ if (css != AT91_PMC_CSS_SLOW) {
+ pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
+ return 0;
+ }
}
}
-#endif
return 1;
}
#include <linux/module.h>
#include <linux/io.h>
#include <linux/mm.h>
+#include <linux/pm.h>
#include <asm/mach/map.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91_pmc.h>
+#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
at91_boot_soc.map_io();
}
+void __iomem *at91_shdwc_base = NULL;
+
+static void at91sam9_poweroff(void)
+{
+ at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+
+void at91_ioremap_shdwc(u32 base_addr)
+{
+ at91_shdwc_base = ioremap(base_addr, 16);
+ if (!at91_shdwc_base)
+ panic("Impossible to ioremap at91_shdwc_base\n");
+ pm_power_off = at91sam9_poweroff;
+}
+
void __init at91_initialize(unsigned long main_clock)
{
at91_boot_soc.ioremap_registers();
projects / karo-tx-linux.git / commitdiff