OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP

Clock source names vary across OMAP2/3 and OMAP4, the clock source enum
names have been made generic in the driver, but for purposes of debugging
and dumping clock sources, it is better to preserve the actual TRM name of
the clock.

Introduce a dss feature function 'dss_feat_get_clk_source_name()' which
returns a string with the TRM clock name for the current OMAP in use. The OMAP
specific name is printed along the generic name within brackets.

Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index a06b2ea41e988d23b23cbff4afc226e74d4f7efa..2c82d9a3df4b1e90587c7cc9d1f8de69c1232aa8 100644 (file)
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2379,14 +2379,15 @@ unsigned long dispc_pclk_rate(enum omap_channel channel)
 void dispc_dump_clocks(struct seq_file *s)
 {
        int lcd, pcd;
+       enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
 
        enable_clocks(1);
 
        seq_printf(s, "- DISPC -\n");
 
-       seq_printf(s, "dispc fclk source = %s\n",
-                       dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
-                       "dss1_alwon_fclk" : "dsi1_pll_fclk");
+       seq_printf(s, "dispc fclk source = %s (%s)\n",
+                       dss_get_generic_clk_source_name(dispc_clk_src),
+                       dss_feat_get_clk_source_name(dispc_clk_src));
 
        seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
 

diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index df35aed828da956a0f23ef9ee3194272848045f5..3ef94227bbe74675ae8f0a0e6d32cea1ce36d4f8 100644 (file)
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -1022,10 +1022,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
 
        DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
 
-       DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
-                       cinfo->regm3, cinfo->dsi1_pll_fclk);
-       DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
-                       cinfo->regm4, cinfo->dsi2_pll_fclk);
+       DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3,
+               dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+               dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+               cinfo->dsi1_pll_fclk);
+       DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4,
+               dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+               dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+               cinfo->dsi2_pll_fclk);
 
        REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
 
@@ -1169,6 +1173,10 @@ void dsi_dump_clocks(struct seq_file *s)
 {
        int clksel;
        struct dsi_clock_info *cinfo = &dsi.current_cinfo;
+       enum dss_clk_source dispc_clk_src, dsi_clk_src;
+
+       dispc_clk_src = dss_get_dispc_clk_source();
+       dsi_clk_src = dss_get_dsi_clk_source();
 
        enable_clocks(1);
 
@@ -1185,23 +1193,27 @@ void dsi_dump_clocks(struct seq_file *s)
        seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
                        cinfo->clkin4ddr, cinfo->regm);
 
-       seq_printf(s,   "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
+       seq_printf(s,   "%s (%s)\t%-16luregm3 %u\t(%s)\n",
+                       dss_get_generic_clk_source_name(dispc_clk_src),
+                       dss_feat_get_clk_source_name(dispc_clk_src),
                        cinfo->dsi1_pll_fclk,
                        cinfo->regm3,
-                       dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ?
+                       dispc_clk_src == DSS_CLK_SRC_FCK ?
                        "off" : "on");
 
-       seq_printf(s,   "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
+       seq_printf(s,   "%s (%s)\t%-16luregm4 %u\t(%s)\n",
+                       dss_get_generic_clk_source_name(dsi_clk_src),
+                       dss_feat_get_clk_source_name(dsi_clk_src),
                        cinfo->dsi2_pll_fclk,
                        cinfo->regm4,
-                       dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
+                       dsi_clk_src == DSS_CLK_SRC_FCK ?
                        "off" : "on");
 
        seq_printf(s,   "- DSI -\n");
 
-       seq_printf(s,   "dsi fclk source = %s\n",
-                       dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ?
-                       "dss1_alwon_fclk" : "dsi2_pll_fclk");
+       seq_printf(s,   "dsi fclk source = %s (%s)\n",
+                       dss_get_generic_clk_source_name(dsi_clk_src),
+                       dss_feat_get_clk_source_name(dsi_clk_src));
 
        seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate());
 
@@ -3235,13 +3247,17 @@ int dsi_init_display(struct omap_dss_device *dssdev)
 void dsi_wait_dsi1_pll_active(void)
 {
        if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
-               DSSERR("DSI1 PLL clock not active\n");
+               DSSERR("%s (%s) not active\n",
+                       dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+                       dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
 }
 
 void dsi_wait_dsi2_pll_active(void)
 {
        if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
-               DSSERR("DSI2 PLL clock not active\n");
+               DSSERR("%s (%s) not active\n",
+                       dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+                       dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
 }
 
 static int dsi_init(struct platform_device *pdev)

diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 998c188c8823fc95729b192706c7ee940fa8384b..d049598bb41247e294c670ca6e050a9c00c92b08 100644 (file)
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -81,6 +81,12 @@ static struct {
        u32             ctx[DSS_SZ_REGS / sizeof(u32)];
 } dss;
 
+static const struct dss_clk_source_name dss_generic_clk_source_names[] = {
+       { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" },
+       { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" },
+       { DSS_CLK_SRC_FCK, "DSS_FCK" },
+};
+
 static void dss_clk_enable_all_no_ctx(void);
 static void dss_clk_disable_all_no_ctx(void);
 static void dss_clk_enable_no_ctx(enum dss_clock clks);
@@ -223,6 +229,11 @@ void dss_sdi_disable(void)
        REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 }
 
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
+{
+       return dss_generic_clk_source_names[clk_src].clksrc_name;
+}
+
 void dss_dump_clocks(struct seq_file *s)
 {
        unsigned long dpll4_ck_rate;
@@ -238,12 +249,16 @@ void dss_dump_clocks(struct seq_file *s)
        seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 
        if (cpu_is_omap3630())
-               seq_printf(s, "dss1_alwon_fclk = %lu / %lu  = %lu\n",
+               seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
+                       dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
+                       dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
                        dpll4_ck_rate,
                        dpll4_ck_rate / dpll4_m4_ck_rate,
                        dss_clk_get_rate(DSS_CLK_FCK));
        else
-               seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n",
+               seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
+                       dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
+                       dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
                        dpll4_ck_rate,
                        dpll4_ck_rate / dpll4_m4_ck_rate,
                        dss_clk_get_rate(DSS_CLK_FCK));

diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index a166ff36ec90b4ee6affd02d7132a5ae1e5f88fb..42ca70f2bfd5428834fd15625a2d4942f1cd6eda 100644 (file)
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -123,6 +123,12 @@ enum dss_clk_source {
        DSS_CLK_SRC_FCK,                        /* DSS1_ALWON_FCLK */
 };
 
+/* Correlates clock source name and dss_clk_source member */
+struct dss_clk_source_name {
+       enum dss_clk_source clksrc;
+       const char *clksrc_name;
+};
+
 struct dss_clock_info {
        /* rates that we get with dividers below */
        unsigned long fck;
@@ -215,6 +221,7 @@ void dss_clk_enable(enum dss_clock clks);
 void dss_clk_disable(enum dss_clock clks);
 unsigned long dss_clk_get_rate(enum dss_clock clk);
 int dss_need_ctx_restore(void);
+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);
 void dss_dump_clocks(struct seq_file *s);
 
 void dss_dump_regs(struct seq_file *s);

diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 3ebe0d91afd2c8859f48f6848e0586dd19b8f048..ccae57b34f5ca06ae1332f2bae397af6e97b600e 100644 (file)
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -25,6 +25,7 @@
 #include <plat/display.h>
 #include <plat/cpu.h>
 
+#include "dss.h"
 #include "dss_features.h"
 
 /* Defines a generic omap register field */
@@ -44,6 +45,7 @@ struct omap_dss_features {
        const unsigned long max_dss_fck;
        const enum omap_display_type *supported_displays;
        const enum omap_color_mode *supported_color_modes;
+       const struct dss_clk_source_name *clksrc_names;
 };
 
 /* This struct is assigned to one of the below during initialization */
@@ -157,6 +159,18 @@ static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
        OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
 };
 
+static const struct dss_clk_source_name omap2_dss_clk_source_names[] = {
+       { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" },
+       { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" },
+       { DSS_CLK_SRC_FCK, "DSS_FCLK1" },
+};
+
+static const struct dss_clk_source_name omap3_dss_clk_source_names[] = {
+       { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" },
+       { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" },
+       { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" },
+};
+
 /* OMAP2 DSS Features */
 static struct omap_dss_features omap2_dss_features = {
        .reg_fields = omap2_dss_reg_fields,
@@ -172,6 +186,7 @@ static struct omap_dss_features omap2_dss_features = {
        .max_dss_fck = 173000000,
        .supported_displays = omap2_dss_supported_displays,
        .supported_color_modes = omap2_dss_supported_color_modes,
+       .clksrc_names = omap2_dss_clk_source_names,
 };
 
 /* OMAP3 DSS Features */
@@ -190,6 +205,7 @@ static struct omap_dss_features omap3430_dss_features = {
        .max_dss_fck = 173000000,
        .supported_displays = omap3430_dss_supported_displays,
        .supported_color_modes = omap3_dss_supported_color_modes,
+       .clksrc_names = omap3_dss_clk_source_names,
 };
 
 static struct omap_dss_features omap3630_dss_features = {
@@ -208,6 +224,7 @@ static struct omap_dss_features omap3630_dss_features = {
        .max_dss_fck = 173000000,
        .supported_displays = omap3630_dss_supported_displays,
        .supported_color_modes = omap3_dss_supported_color_modes,
+       .clksrc_names = omap3_dss_clk_source_names,
 };
 
 /* OMAP4 DSS Features */
@@ -224,6 +241,7 @@ static struct omap_dss_features omap4_dss_features = {
        .max_dss_fck = 186000000,
        .supported_displays = omap4_dss_supported_displays,
        .supported_color_modes = omap3_dss_supported_color_modes,
+       .clksrc_names = omap3_dss_clk_source_names,
 };
 
 /* Functions returning values related to a DSS feature */
@@ -260,6 +278,11 @@ bool dss_feat_color_mode_supported(enum omap_plane plane,
                        color_mode;
 }
 
+const char *dss_feat_get_clk_source_name(enum dss_clk_source id)
+{
+       return omap_current_dss_features->clksrc_names[id].clksrc_name;
+}
+
 /* DSS has_feature check */
 bool dss_has_feature(enum dss_feat_id id)
 {

diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 18ab195158178cef48521744a3fbeae0f740524e..65d6de7e0feb7be99defaf8ae4fc8112d1d5bf46 100644 (file)
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -57,6 +57,7 @@ enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel
 enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
 bool dss_feat_color_mode_supported(enum omap_plane plane,
                enum omap_color_mode color_mode);
+const char *dss_feat_get_clk_source_name(enum dss_clk_source id);
 
 bool dss_has_feature(enum dss_feat_id id);
 void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);