ENGR00222835 MX6x-Fix incorrect enabling/disabling of PLL1

PLL1 was enabled without incrementing the usecount, and was
thus not getting disabled under certain conditions.
This causes 2 issues:
1. Increases the power.
2. Causes crashes on MX6SL in audio mode as ARM is switched
to PLL1 assuming its in bypass when entering WAIT mode. But PLL1
is enabled and not in bypass state.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 8b75aee7896490d6902b188fed0fc9bb65636eb0..a3dc7e4aeb1e93561c295bda6f641ae80db9febf 100644 (file)
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -1334,9 +1334,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
                spin_unlock_irqrestore(&clk_lock, flags);
                return -1;
        }
-       /* Need PLL1-MAIN to be ON to write to ARM-PODF bit. */
-       if (!pll1_enabled)
-               pll1_sys_main_clk.enable(&pll1_sys_main_clk);
 
        cur_arm_podf = div;
 

diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 6bd818ae71394500942cc9da0c35d1b8d3ffcbb0..08212c3c3ecb9c9219e1a1d619e7c5e9cc9fe7bb 100755 (executable)
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -1239,9 +1239,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
                return -1;
        }
 
-       if (!pll1_enabled)
-               pll1_sys_main_clk.enable(&pll1_sys_main_clk);
-
        cur_arm_podf = div;
 
        __raw_writel(div - 1, MXC_CCM_CACRR);